Intel N450 AU80610004653AA User Manual

Product codes
AU80610004653AA
Page of 85
Datasheet
41
Electrical Specifications
4.8
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) 
logic, Intel recommends the processor be first in the TAP chain, followed by any other 
components within the system. A translation buffer should be used to connect to the 
rest of the chain unless one of the other components is capable of accepting an input of 
the appropriate voltage. Two copies of each signal may be required with each driving a 
different voltage level.
4.9
Absolute Maximum and Minimum Ratings
 specifies absolute maximum and minimum ratings. At conditions outside 
functional operation condition limits, but within absolute maximum and minimum 
ratings, neither functionality nor long-term reliability can be expected. If a device is 
returned to conditions within functional operation limits after having been subjected to 
conditions outside these limits (but within the absolute maximum and minimum 
ratings) the device may be functional, but with its lifetime degraded depending on 
exposure to conditions exceeding the functional operation condition limits.
Although the processor contains protective circuitry to resist damage from Electro-
Static Discharge (ESD), precautions should always be taken to avoid high static 
voltages or electric fields
Table 4-20.Processor Absolute Minimum and Maximum Ratings  (Sheet 1 of 2)
Symbol
Parameter
Min
Max
Unit
Notes
1, 2
V
CC
, V
CCP
Processor Core, LGI voltages 
with respect to V
SS
-0.3
1.45
V
6
V
CCSM, 
V
CCCK_DDR
Processor DDR voltage with 
respect to V
SS
-0.3
2.25
V
V
CCA
Processor PLL voltage with 
respect to V
SS
-0.3
2.25
V
V
CCGFX
Processor GFX voltage with 
respect to V
SS
-0.3
1.55
V
V
CCLVDS
Processor LVDS voltage with 
respect to V
SS
-0.3
2.25
V
V
CCA_DDR, 
V
CCACK_DDR
Processor DDR PLL voltage 
with respect to V
SS
-0.3
1.45
V
V
CCRING_EAST, 
V
CCRING_WEST, 
V
CC_LGI_VID, 
Processor DAC, LGIO, LVDS, & 
LGIO voltage with respect to 
V
SS
-0.3
1.45
V
V
CCD_AB_DPL, 
V
CCD_HMPLL
Processor DPLL, & HMPLL 
voltage with respect to V
SS
-0.3
1.45
V
V
CCSFR_AB_DPL,
Processor SFR DPLL voltage 
with respect to V
SS
-0.3
2.25
V
V
CCACRTDAC
Processor CRT DAC voltage 
with respect to V
SS
-0.3
2.25
V