Intel i7-950 AT80601002112AA User Manual

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Datasheet 

DDR{0/1/2}_MA[15:0]

O

Selects the Row address for Reads and writes, and the column address for 

activates. Also used to set values for DRAM configuration registers.

DDR{0/1/2}_ODT[3:0]

O

Enables various combinations of termination resistance in the target and non-

target DIMMs when data is read or written

DDR{0/1/2}_RAS#

O

Row Address Strobe.

DDR{0/1/2}_RESET#

O

Resets DRAMs. Held low on power up, held high during self refresh, otherwise 

controlled by configuration register.

DDR{0/1/2}_WE#

O

Write Enable.

ISENSE

I

Current sense from VRD11.1.

PECI

I/O

PECI (Platform Environment Control Interface) is the serial sideband interface to 

the processor and is used primarily for thermal, power and error management. 

Details regarding the PECI electrical specifications, protocols and functions can 

be found in the Platform Environment Control Interface Specification. 

PRDY#

O

PRDY# is a processor output used by debug tools to determine processor debug 

readiness.

PREQ#

I/O

PREQ# is used by debug tools to request debug operation of the processor.

PROCHOT#

I/O

PROCHOT# will go active when the processor temperature monitoring sensor 

detects that the processor has reached its maximum safe operating 

temperature. This indicates that the processor Thermal Control Circuit has been 

activated, if enabled. This signal can also be driven to the processor to activate 

the Thermal Control Circuit. This signal does not have on-die termination and 

must be terminated on the system board.

PSI#

O

Processor Power Status Indicator signal. This signal is asserted when maximum 

possible processor core current consumption is less than 20A. Assertion of this 

signal is an indication that the VR controller does not currently need to be able 

to provide ICC above 20A, and the VR controller can use this information to 

move to more efficient operation point. This signal will de-assert at least 3.3 us 

before the current consumption will exceed 20A. The minimum PSI# 

assertion and de-assertion time is 1 BCLK.

RESET#

I

Asserting the RESET# signal resets the processor to a known state and 

invalidates its internal caches without writing back any of their contents. Note 

some PLL, QPI and error states are not effected by reset and only 

VCCPWRGOOD forces them to a known state. For a power-on Reset, RESET# 

must stay active for at least one millisecond after VCC and BCLK have reached 

their proper specifications. RESET# must not be kept asserted for more than 

10 ms while VCCPWRGOOD is asserted. RESET# must be held  de-asserted for 

at least 1 ms before it is asserted again. RESET# must be held asserted before 

VCCPWRGOOD is asserted. This signal does not have on-die termination and 

must be terminated on the system board. RESET# is a common clock signal.

SKTOCC#

O

SKTOCC# (Socket Occupied) will be pulled to ground on the processor package. 

There is no connection to the processor silicon for this signal. System board 

designers may use this signal to determine if the processor is present.

TCK

I

TCK (Test Clock) provides the clock input for the processor Test Bus (also known 

as the Test Access Port).

TDI

I

TDI (Test Data In) transfers serial test data into the processor. TDI provides the 

serial input needed for JTAG specification support.

TDO

O

TDO (Test Data Out) transfers serial test data out of the processor. TDO 

provides the serial output needed for JTAG specification support.

TESTLOW

I

TESTLOW must be connected to ground through a resistor for proper processor 

operation.