Intel i7-950 AT80601002112AA User Manual
Product codes
AT80601002112AA
Datasheet
83
Features
7
Features
7.1
Power-On Configuration (POC)
Several configuration options can be configured by hardware. For electrical
specifications on these options, refer to
specifications on these options, refer to
. Note that request to execute BIST is
not selected by hardware but is passed across the Intel QPI link during initialization.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor; for reset purposes, the processor does not distinguish between a
"warm" reset and a “power-on” reset.
configuration options cannot be changed except by another reset. All resets reconfigure
the processor; for reset purposes, the processor does not distinguish between a
"warm" reset and a “power-on” reset.
Notes:
1.
Latched when VTTPWRGOOD is asserted and all internal power good conditions are met.
2.
See the signal definitions in
Table 6-1
for the description of MSID and CSC.
7.2
Clock Control and Low Power States
The processor supports low power states at the individual thread, core, and package
level for optimal power management. The processor implements software interfaces for
requesting low power states: MWAIT instruction extensions with sub-state hints, the
HLT instruction (for C1 and C1E) and P_LVLx reads to the ACPI P_BLK register block
mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to
equivalent MWAIT C-state requests inside the processor and do not directly result in
I/O reads to the system. The P_LVLx I/O Monitor address does not need to be set up
before using the P_LVLx I/O read interface.
level for optimal power management. The processor implements software interfaces for
requesting low power states: MWAIT instruction extensions with sub-state hints, the
HLT instruction (for C1 and C1E) and P_LVLx reads to the ACPI P_BLK register block
mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to
equivalent MWAIT C-state requests inside the processor and do not directly result in
I/O reads to the system. The P_LVLx I/O Monitor address does not need to be set up
before using the P_LVLx I/O read interface.
Software may make C-state requests by using a legacy method involving I/O reads
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This
feature is designed to provide legacy support for operating systems that initiate C-state
transitions using access to pre-defined ICH registers. The base P_LVLx register is
P_LVL2, corresponding to a C3 request; P_LVL3 is C6.
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This
feature is designed to provide legacy support for operating systems that initiate C-state
transitions using access to pre-defined ICH registers. The base P_LVLx register is
P_LVL2, corresponding to a C3 request; P_LVL3 is C6.
P_LVLx is limited to a subset of C-states. For Example, P_LVL8 is not supported and will
not cause an I/O redirection to a C8 request. Instead, it will fall through like a normal
I/O instruction. The range of I/O addresses that may be converted into C-state
requests is also defined in the PMG_IO_CAPTURE MSR, in the ‘C-state Range’ field. This
field maybe written by BIOS to restrict the range of I/O addresses that are trapped and
redirected to MWAIT instructions. Note that when I/O instructions are used, no MWAIT
substates can be defined, as therefore the request defaults to have a sub-state or zero,
but always assumes the ‘break on IF==0’ control that can be selected using ECX with
an MWAIT instruction.
not cause an I/O redirection to a C8 request. Instead, it will fall through like a normal
I/O instruction. The range of I/O addresses that may be converted into C-state
requests is also defined in the PMG_IO_CAPTURE MSR, in the ‘C-state Range’ field. This
field maybe written by BIOS to restrict the range of I/O addresses that are trapped and
redirected to MWAIT instructions. Note that when I/O instructions are used, no MWAIT
substates can be defined, as therefore the request defaults to have a sub-state or zero,
but always assumes the ‘break on IF==0’ control that can be selected using ECX with
an MWAIT instruction.
Table 7-1.
Power On Configuration Signal Options
Configuration Option
Signal
MSID
VID[2:0]/MSID[2:0]
1, 2
CSC
VID[5:3]/CSC[2:0]
1, 2