Renesas rl78 User Manual
13.5.3 Transfer
direction specification ................................................................................................... 591
13.5.4 Acknowledge (ACK).................................................................................................................... 592
13.5.5 Stop
condition ............................................................................................................................. 593
13.5.6 Wait ............................................................................................................................................ 594
13.5.7 Canceling wait ............................................................................................................................ 596
13.5.8 Interrupt request (INTIICA0) generation timing and wait control ................................................. 597
13.5.9 Address
match detection method ............................................................................................... 598
13.5.10 Error detection ............................................................................................................................ 598
13.5.11 Extension code ........................................................................................................................... 598
13.5.12 Arbitration ................................................................................................................................... 599
13.5.13 Wakeup function ......................................................................................................................... 601
13.5.14 Communication reservation ........................................................................................................ 604
13.5.15 Cautions...................................................................................................................................... 608
13.5.16 Communication operations ......................................................................................................... 609
13.5.17 Timing of I
2
C interrupt request (INTIICA0) occurrence................................................................ 616
13.6 Timing
Charts .......................................................................................................................... 637
CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR ....................................... 652
14.1 Functions of Multiplier and Divider/Multiply-Accumulator ................................................. 652
14.2 Configuration of Multiplier and Divider/Multiply-Accumulator .......................................... 652
14.2.1 Multiplication/division
data register A (MDAH, MDAL) ................................................................ 654
14.2.2 Multiplication/division
data register B (MDBL, MDBH) ................................................................ 655
14.2.3 Multiplication/division
data register C (MDCL, MDCH) ............................................................... 656
14.3 Register Controlling Multiplier and Divider/Multiply-Accumulator.................................... 658
14.3.1 Multiplication/division control register (MDUC) ........................................................................... 658
14.4 Operations of Multiplier and Divider/Multiply-Accumulator ............................................... 660
14.4.1 Multiplication
(unsigned) operation ............................................................................................. 660
14.4.2 Multiplication
(signed) operation ................................................................................................. 661
14.4.3 Multiply-accumulation (unsigned) operation................................................................................ 662
14.4.4 Multiply-accumulation (signed) operation.................................................................................... 664
14.4.5 Division
operation ....................................................................................................................... 666
CHAPTER 15 DMA CONTROLLER ..................................................................................................... 668
15.1 Functions
of
DMA
Controller ................................................................................................. 668
15.2 Configuration of DMA Controller........................................................................................... 669
15.2.1 DMA SFR address register n (DSAn) ......................................................................................... 669
15.2.2 DMA RAM address register n (DRAn) ........................................................................................ 670
15.2.3 DMA byte count register n (DBCn) ............................................................................................. 671
15.3 Registers Controlling DMA Controller .................................................................................. 672
15.3.1 DMA mode control register n (DMCn)......................................................................................... 672
15.3.2 DMA operation control register n (DRCn) ................................................................................... 674
15.4 Operation of DMA Controller ................................................................................................. 675
15.4.1 Operation procedure ................................................................................................................... 675
15.4.2 Transfer mode ............................................................................................................................ 676
15.4.3 Termination
of DMA transfer....................................................................................................... 676
15.5 Example of Setting of DMA Controller .................................................................................. 677
Index-9