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Renesas rl78 User Manual

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RL78/G1A 
 
CHAPTER  5   CLOCK  GENERATOR 
R01UH0305EJ0200  Rev.2.00 
 
 
147  
Jul 04, 2013 
5.3.3  Clock operation status control register (CSC) 
This register is used to control the operations of the high-speed system clock, high-speed on-chip oscillator clock, and 
subsystem clock (except the low-speed on-chip oscillator clock). 
The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction. 
Reset signal generation sets this register to C0H. 
 
Figure 5-4.  Format of Clock Operation Status Control Register (CSC)  
 
Address:  FFFA1H     After reset:  C0H     R/W 
Symbol 
<7> 
<6> 
5 4 3 2 1 
<0> 
CSC 
MSTOP 
XTSTOP 
0 0 0 0 0 
HIOSTOP
 
 
High-speed system clock operation control 
 
MSTOP 
X1 oscillation mode 
External clock input mode 
Input port mode 
 
0 
X1 oscillator operating 
External clock from EXCLK 
pin is valid 
 
1 
X1 oscillator stopped 
External clock from EXCLK 
pin is invalid 
Input port 
 
 
Subsystem clock operation control 
 
XTSTOP 
XT1 oscillation mode 
External clock input mode 
Input port mode 
 
0 
XT1 oscillator operating 
External clock from EXCLKS 
pin is valid 
 
1 
XT1 oscillator stopped 
External clock from EXCLKS 
pin is invalid 
Input port 
 
 
HIOSTOP 
High-speed on-chip oscillator clock operation control 
 0 
High-speed 
on-chip oscillator operating 
 
1 
High-speed on-chip oscillator stopped 
 
Cautions 1.  After reset release, set the clock operation mode control register (CMC) before 
setting the CSC register. 
 
2.  Set the oscillation stabilization time select register (OSTS) before setting the MSTOP 
bit to 0 after releasing reset.  Note that if the OSTS register is being used with its 
default settings, the OSTS register is not required to be set here. 
 
3.  To start X1 oscillation as set by the MSTOP bit, check the oscillation stabilization 
time of the X1 clock by using the oscillation stabilization time counter status register 
(OSTC). 
 
4.  When starting XT1 oscillation by setting the XTSTOP bit, wait for oscillation of the 
subsystem clock to stabilize by setting a wait time using software. 
 
5.  Do not stop the clock selected for the CPU peripheral hardware clock (f
CLK
) with the 
OSC register.  
 
6.  The setting of the flags of the register to stop clock oscillation (invalidate the 
external clock input) and the condition before clock oscillation is to be stopped are 
as Table 5-2.