Renesas rl78 User Manual

Page of 1004
 
RL78/G1A 
 
CHAPTER  5   CLOCK  GENERATOR 
R01UH0305EJ0200  Rev.2.00 
 
 
149  
Jul 04, 2013 
Figure 5-5.  Format of Oscillation Stabilization Time Counter Status Register (OSTC)  
 
Address:  FFFA2H     After reset:  00H     R 
Symbol 
7 6 5 4 3 2 1 0 
 
OSTC MOST
MOST
MOST
10 
MOST
11 
MOST
13 
MOST
15 
MOST
17 
MOST
18 
 
 
Oscillation stabilization time status 
MOST
MOST
MOST
10 
MOST
11 
MOST
13 
MOST
15 
MOST
17 
MOST
18 
 
f
X
 = 10 MHz 
f
X
 = 20 MHz
0 0 0 0 0 0 0 0 
2
8
/f
X
 max.
25.6 
μs max.  12.8 μs max.
1 0 0 0 0 0 0 0 
2
8
/f
X
 min.
25.6 
μs min.  12.8 μs min.
1 1 0 0 0 0 0 0 
2
9
/f
X
 min.
51.2 
μs min.  25.6 μs min.
1 1 1 0 0 0 0 0 
2
10
/f
X
 min.
102 
μs min.  51.2 μs min.
1 1 1 1 0 0 0 0 
2
11
/f
X
 min.
204 
μs min.  102 μs min.
1 1 1 1 1 0 0 0 
2
13
/f
X
 min.
819 
μs min.  409 μs min.
1 1 1 1 1 1 0 0 
2
15
/f
X
 min.
3.27 ms min.  1.63 ms min.
1 1 1 1 1 1 1 0 
2
17
/f
X
 min.
13.1 ms min.  6.55 ms min.
1 1 1 1 1 1 1 1 
2
18
/f
X
 min.
26.2 ms min.  13.1 ms min.
 
Cautions 1.  After the above time has elapsed, the bits are set to 1 in order from the MOST8 bit 
and remain 1. 
 
2.  The oscillation stabilization time counter counts up to the oscillation stabilization 
time set by the oscillation stabilization time select register (OSTS).   
 
 
In the following cases, set the oscillation stabilization time of the OSTS register to 
the value greater than the count value which is to be checked by the OSTC register. 
 
•  If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or 
subsystem clock is being used as the CPU clock. 
•  If the STOP mode is entered and then released while the high-speed on-chip 
oscillator clock is being used as the CPU clock with the X1 clock oscillating.  
(Note, therefore, that only the status up to the oscillation stabilization time set by 
the OSTS register is set to the OSTC register after the STOP mode is released.) 
 
 
3.  The X1 clock oscillation stabilization wait time does not include the time until clock 
oscillation starts (“a” below). 
 
STOP mode release
X1 pin voltage 
waveform
a
 
 
Remark  f
X
: X1 clock oscillation frequency 
 
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