Renesas rl78 User Manual

Page of 1004
 
RL78/G1A 
 
CHAPTER  5   CLOCK  GENERATOR 
R01UH0305EJ0200  Rev.2.00 
 
 
151  
Jul 04, 2013 
Figure 5-6.  Format of Oscillation Stabilization Time Select Register (OSTS) 
Address:  FFFA3H     After reset:  07H     R/W 
Symbol 
7 6 5 4 3 2 1 0 
OSTS 
0 0 0 0 0 
OSTS2 
OSTS1 
OSTS0 
 
 
Oscillation stabilization time selection 
 
OSTS2 OSTS1 OSTS0 
 
f
X
 = 10 MHz 
f
X
 = 20 MHz 
 0 0 0 
2
8
/f
X
 25.6 
μs 12.8 
μs 
 0 0 1 
2
9
/f
X
 51.2 
μs 25.6 
μs 
 0 1 0 
2
10
/f
X
 102 
μs 51.2 
μs 
 0 1 1 
2
11
/f
X
 204 
μs 102 
μs 
 1 0 0 
2
13
/f
X
 819 
μs 409 
μs 
 1 0 1 
2
15
/f
X
 
3.27 ms 
1.63 ms 
 1 1 0 
2
17
/f
X
 
13.1 ms 
6.55 ms 
 1 1 1 
2
18
/f
X
 
26.2 ms 
13.1 ms 
Cautions 1.  Change the setting of the OSTS register before setting the MSTOP bit of the clock 
operation status control register (CSC) to 0. 
 
2.  The oscillation stabilization time counter counts up to the oscillation stabilization 
time set by the OSTS register.  
 
 
In the following cases, set the oscillation stabilization time of the OSTS register to 
the value greater than the count value which is to be checked by the OSTC register 
after the oscillation starts. 
 
•  If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or 
subsystem clock is being used as the CPU clock. 
•  If the STOP mode is entered and then released while the high-speed on-chip 
oscillator clock is being used as the CPU clock with the X1 clock oscillating. (Note, 
therefore, that only the status up to the oscillation stabilization time set by the 
OSTS register is set to the OSTC register after the STOP mode is released.) 
 
 
3.  The X1 clock oscillation stabilization wait time does not include the time until clock 
oscillation starts (“a” below). 
 
STOP mode release
X1 pin voltage 
waveform
a
 
 
Remark  f
X
: X1 clock oscillation frequency 
 
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