Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  6   TIMER  ARRAY  UNIT 

R01UH0305EJ0200  Rev.2.00 

 

 

219  

Jul 04, 2013 

 

When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly 

counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply. 

 

(1)   Only an even channel (channel 0, 2, 4, etc.) can be set as a master channel. 

(2)   Any channel, except channel 0, can be set as a slave channel. 

(3)   The slave channel must be lower than the master channel. 

Example:   If channel 2 is set as a master channel, channel 3 or those that follow (channels 3, 4, 5, etc.) can be set 

as a slave channel. 

 

(4)   Two or more slave channels can be set for one master channel. 

(5)   When two or more master channels are to be used, slave channels with a master channel between them may not 

be set. 

Example:   If channels 0 and 4 are set as master channels, channels 1 to 3 can be set as the slave channels of 

master channel 0.  Channels 5 to 7 cannot be set as the slave channels of master channel 0. 

 

(6)  The operating clock for a slave channel in combination with a master channel must be the same as that of the 

master channel.  The CKSmn0, CKSmn1 bits (bit 15, 14 of timer mode register mn (TMRmn)) of the slave channel 

that operates in combination with the master channel must be the same value as that of the master channel. 

(7)   A master channel can transmit INTTMmn (interrupt), start software trigger, and count clock to the lower channels. 

(8)   A slave channel can use INTTMmn (interrupt), a start software trigger, or the count clock of the master channel as 

a source clock, but cannot transmit its own INTTMmn (interrupt), start software trigger, or count clock to channels 

with lower channel numbers. 

(9)   A master channel cannot use INTTMmn (interrupt), a start software trigger, or the count clock from the other higher 

master channel as a source clock. 

(10) To simultaneously start channels that operate in combination, the channel start trigger bit (TSmn) of the channels 

in combination must be set at the same time. 

(11) During the counting operation, a TSmn bit of a master channel or TSmn bits of all channels which are operating 

simultaneously can be set.  It cannot be applied to TSmn bits of slave channels alone. 

(12) To stop the channels in combination simultaneously, the channel stop trigger bit (TTmn) of the channels in 

combination must be set at the same time. 

(13) CKm2/CKm3 cannot be selected while channels are operating simultaneously, because the operating clocks of 

master channels and slave channels have to be synchronized. 

(14) Timer mode register m0 (TMRm0) has no master bit (it is fixed as “0”).  However, as channel 0 is the highest 

channel, it can be used as a master channel during simultaneous operation. 

 

The rules of the simultaneous channel operation function are applied in a channel group (a master channel and slave 

channels forming one simultaneous channel operation function). 

If two or more channel groups that do not operate in combination are specified, the basic rules of the simultaneous 

channel operation function in 6.4.1  Basic rules of simultaneous channel operation function do not apply to the 

channel groups. 

 

Remark  m: Unit number (m = 0), n: Channel number (n = 0 to 7 (however, timer input pin (TImn), timer output pin 

(TOmn) : n = 0, 1, 3 to 7))