Renesas rl78 User Manual

RL78/G1A

CHAPTER 6 TIMER ARRAY UNIT

R01UH0305EJ0200 Rev.2.00

233

Jul 04, 2013

(2) Default level of TOmn pin and output level after timer operation start

The change in the output level of the TOmn pin when timer output register m (TOm) is written while timer output is

disabled (TOEmn = 0), the initial level is changed, and then timer output is enabled (TOEmn = 1) before port

output is enabled, is shown below.

(a) When operation starts with master channel output mode (TOMmn = 0) setting

The setting of timer output level register m (TOLm) is invalid when master channel output mode (TOMmn = 0).

When the timer operation starts after setting the default level, the toggle signal is generated and the output

level of the TOmn pin is reversed.

Figure 6-32. TOmn Pin Output Status at Toggle Output (TOMmn = 0)

TOE

TOmn

(output)

TOmn bit = 0
(Default status : Low)

Default
status

Port output is enabled

Toggle

Bold : Active level

TOmn bit = 1
(Default status : High)

TOmn bit = 0
(Default status : Low)

TOmn bit = 1
(Default status : High)

TOmn bit = 0
(Active high)

TOmn bit = 1
(Active low)

Remarks 1. Toggle: Reverse TOmn pin output status

2. m: Unit number (m = 0), n: Channel number (n = 0, 1, 3 to 7)