Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  1   OUTLINE 

 

 

PORT 1

P10 to P12

PORT 2

P20 to P23

4

PORT 3

P30, P31

2

PORT 4

PORT 5

3

PORT 12

P121, P122

P40

VOLTAGE
REGULATOR

REGC

INTERRUPT

CONTROL

RAM

POWER ON RESET/

VOLTAGE 

DETECTOR

POR/LVD

CONTROL

RESET CONTROL

SYSTEM

CONTROL

RESET

X1/P121

X2/EXCLK/P122

HIGH-SPEED

ON-CHIP

OSCILLATOR

ON-CHIP DEBUG

TOOL0/P40

SERIAL ARRAY
   UNIT0 (4ch)

UART0

UART1

IIC00

RxD0/P11
TxD0/P12

RxD1/P03

TxD1/P02

SCL00/P10

SDA00/P11

TIMER ARRAY
   UNIT (8ch)

ch2

ch3

TI03/TO03/P31

ch0

ch1

ch4

ch5

ch6

ch7

INTP0/P137

INTP3/P30,
INTP4/P31 

INTP1/P50

A/D CONVERTER

4

ANI0/P20 to 
ANI3/P23 

AV

REFP

/P20

AV

REFM

/P21

2

PORT 13

P137

CSI11

SCK11/P30

SO11/P51

SI11/P50

IIC11

SCL11/P30

SDA11/P50

TI00/P02

TO00/P03

BCD 

ADJUSTMENT

SCK00/P10

SO00/P12

SI00/P11

CSI00

V

SS

AV

SS

TOOLRxD/P11, 
TOOLTxD/P12

V

DD

AV

DD

SERIAL
INTERFACE IICA0

SDAA0/P61

SCLA0/P60

2

INTP2/P51

MULTIPLIER&

DIVIDER, 

MULITIPLY-

ACCUMULATOR

PORT 0

P02, P03

2

9

ANI16/P03, ANI17/P02, 
ANI18/P10, ANI20/P11,
ANI21/P12, ANI25/P51,
ANI26/P50, ANI27/P30,
ANI29/P31

DIRECT MEMORY
ACCESS CONTROL

PORT 6

P60, P61

2

BUZZER OUTPUT

PCLBUZ0/P31

CLOCK OUTPUT
CONTROL

WINDOW

WATCHDOG

TIMER

REAL-TIME

CLOCK

RL78

CPU

CORE

CODE FLASH MEMORY

DATA FLASH MEMORY

INTERVAL

TIMER

P50, P51

2

(KEY RETURN)

(4)

(KR0/P02, KR1/P03,
KR2/P22, KR3/P23)

CRC

LOW-SPEED

ON-CHIP

OSCILLATOR

 

 

Remark  Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection 

register (PIOR).  See Figure 4-8  Format of Peripheral I/O Redirection Register (PIOR). 

 

R01UH0305EJ0200  Rev.2.00 

 

 

13  

Jul 04, 2013