Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  7   REAL-TIME  CLOCK 

Perform one of the following processing when shifting to HALT/STOP mode immediately after setting the RTCE bit to 1. 

However, after setting the RTCE bit to 1, this processing is not required when shifting to HALT/STOP mode after the 

INTRTC interrupt has occurred. 

 

•  Shifting to HALT/STOP mode when at least two count clocks (f

RTC

) have elapsed after setting the RTCE bit to 1 

(see Figure 7-20, Example 1). 

•  Checking by polling the RWST bit to become 1, after setting the RTCE bit to 1 and then setting the RWAIT bit to 1.  

Afterward, setting the RWAIT bit to 0 and shifting to HALT/STOP mode after checking again by polling that the 

RWST bit has become 0 (see Figure 7-20, Example 2). 

 

Yes

RTCE = 1 

RWAIT = 1 

No

Yes

RWAIT = 0 

No

RWST = 1?

RWST = 0?

HALT/STOP instruction 

execution

RTCE = 1 

HALT/STOP instruction 

execution 

Waiting at least for 2 

f

RTC

 clocks 

Sets to counter operation 

start 

Shifts to HALT/STOP 

mode 

Sets to counter operation 

start 

Sets to stop the SEC to YEAR 

counters, reads the counter 

value, write mode 

Checks the counter wait status 

 

Sets the counter operation 

Shifts to HALT/STOP 

mode 

Example 1 

Example 2 

 

 

R01UH0305EJ0200  Rev.2.00 

 

 

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Jul 04, 2013