Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  1   OUTLINE 

<R> 

PORT 1

P10 to P15

PORT 2

P20 to P24

5

PORT 3

P30, P31

2

PORT 4

PORT 5

6

PORT 12

P121, P122

P40

P50, P51

2

VOLTAGE
REGULATOR

REGC

INTERRUPT

CONTROL

RAM

POWER ON RESET/

VOLTAGE 

DETECTOR

POR/LVD

CONTROL

RESET CONTROL

SYSTEM

CONTROL

RESET

X1/P121

X2/EXCLK/P122

HIGH-SPEED

ON-CHIP

OSCILLATOR

ON-CHIP DEBUG

TOOL0/P40

SERIAL ARRAY
   UNIT0 (4ch)

UART0

UART1

IIC00

RxD0/P11

TxD0/P12

RxD1/P03

TxD1/P02

SCL00/P10

SDA00/P11

TIMER ARRAY
   UNIT (8ch)

ch2

ch3

TI03/TO03/P31

ch0

ch1

ch4

ch5

ch6

ch7

2

INTP0/P137

INTP3/P30,
INTP4/P31 

INTP1/P50,
INTP2/P51 

RxD2/P14

A/D CONVERTER

5

ANI0/P20 to 
ANI4/P24 

AV

REFP

/P20

AV

REFM

/P21

2

P120

PORT 13

P137

CSI11

SCK11/P30

SO11/P51

SI11/P50

IIC11

SCL11/P30

SDA11/P50

TI00/P02

TO00/P03

BCD 

ADJUSTMENT

SCK00/P10

SO00/P12

SI00/P11

CSI00

V

SS

,

AV

SS

TOOLRxD/P11, 
TOOLTxD/P12

V

DD

,

AV

DD

SERIAL
INTERFACE IICA0

SDAA0/P61

SCLA0/P60

2

MULTIPLIER&

DIVIDER, 

MULITIPLY-

ACCUMULATOR

PORT 0

P02, P03

2

BUZZER OUTPUT

CLOCK OUTPUT
CONTROL

13

ANI16/P01, ANI17/P00, ANI18/P10, 
ANI19/P120 to ANI24/P15, ANI26/P50, 
ANI27/P30, ANI28/P70, ANI29/P31

SERIAL ARRAY
   UNIT1 (2ch)

UART2

LINSEL

IIC20

RxD2/P14
TxD2/P13

SCL20/P15

SDA20/P14

SCK20/P15

SO20/P13

SI20/P14

CSI20

DIRECT MEMORY
ACCESS CONTROL

PORT 6

PORT 7

P70

P60 to P62

3

PCLBUZ0/P31, 
PCLBUZ1/P15

2

WINDOW

WATCHDOG

TIMER

LOW-SPEED

ON-CHIP

OSCILLATOR

REAL-TIME

CLOCK

RL78

CPU

CORE

CODE FLASH MEMORY

DATA FLASH MEMORY

INTERVAL

TIMER

KEY RETURN

1(6)

KR0/P70
(KR0/P10 to KR5/P15)
(KR0/P120, KR1/P02, KR2/P03,
KR3/P22 to KR5/P24)

RxD2/P14

CRC

 

 

Remark  Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection 

register (PIOR).  See Figure 4-8  Format of Peripheral I/O Redirection Register (PIOR). 

 

R01UH0305EJ0200  Rev.2.00 

 

 

14  

Jul 04, 2013