Renesas rl78 User Manual

 

RL78/G1A 

CHAPTER  9   CLOCK  OUTPUT/BUZZER  OUTPUT  CONTROLLER 

 

One pin can be used to output a clock or buzzer sound. 

The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0). 

The PCLBUZ1 pin outputs a clock/buzzer selected by the clock output select register 1 (CKS1). 

 

The PCLBUZn pin is output as the following procedure. 

 

<1>  Set 0 in the bit of the port mode register (PMxx) and port register (Pxx) which correspond to the port which has a 

pin used as the PCLBUZn pin. 

<R> 

<2>  Select the output frequency with bits 0 to 3 (CCSn0 to CCSn2, CSELn) of the clock output select register (CKSn) 

of the PCLBUZn pin (output in disabled status).  

<3>  Set bit 7 (PCLOEn) of the CKSn register to 1 to enable clock/buzzer output.  

 

Remarks 1. The controller used for outputting the clock starts or stops outputting the clock one clock after enabling or 

disabling clock output (PCLOEn bit) is switched.  At this time, pulses with a narrow width are not output.  

Figure 9-3 shows enabling or stopping output using the PCLOEn bit and the timing of outputting the clock. 

n = 0, 1 

<R> 

 

PCLOEn

1 clock elapsed

Narrow pulses are not output

Clock output

 

 

 

 

When the main system clock is selected for the PCLBUZn output (CSEL = 0), if STOP or HALT mode is entered within 

1.5 clock cycles output from the PCLBUZn pin after the output is disabled (PCLOEn = 0), the PCLBUZn output width 

becomes shorter. 

<R> 

 

 

R01UH0305EJ0200  Rev.2.00 

 

 

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Jul 04, 2013