Renesas rl78 User Manual
RL78/G1A
CHAPTER 11 A/D CONVERTER
R01UH0305EJ0200 Rev.2.00
362
Jul 04, 2013
11.3.5 12-bit A/D conversion result register (ADCR)
This register is a 16-bit register that stores the A/D conversion result. The higher 4 bits are fixed to 0. Each time A/D
conversion ends, each time A/D conversion ends, the value of ADSAR [11:0] is stored in the A/D conversion result register
(note that whether to store this value is determined by the setting of the ADRCK bit of the ADM2 register and by the
settings of the ADUL and ADLL registers). The higher 4 bits of the conversion result are stored in FFF1FH and the lower
8 bits are stored in the lower 4 bits of FFF1EH
Note
.
The ADCR register can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Note If the A/D conversion result is outside the range specified by using the A/D conversion comparison function (the
value specified by the ADRCK bit of the ADM2 register and ADUL/ADLL registers; see Figure 11-8), the result is
not stored.
Caution The valid resolution differs depending on the voltage conditions of AV
DD
and AV
REFP
.
For details, see 29.6.1 A/D converter characteristics.
Remarks 1. When using the converter with a resolution of 10 bits, select the 12-bit resolution mode (ADTYP = 0). Use
the higher 10 bits of the conversion result. Do not use the lower 2 bits.
2. When using the converter with a resolution of 8 bits, select the 8-bit resolution mode (ADTYP = 1). Do
not use the lower 4 bits of the ADCR register.
The higher 8 bits of the conversion result can be read by using the ADCRH register.
Figure 11-9. Format of 12-bit A/D Conversion Result Register (ADCR)
Symbol
Address: FFF1EH, FFF1FH After reset: 0000H R
FFF1FH
FFF1EH
0
0
0
0
ADCR
Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of the ADCR register
may become undefined. Read the conversion result following conversion completion before
writing to the ADM0, ADS, and ADPC registers. Using timing other than the above may cause an
incorrect conversion result to be read.
2.
If INTAD does not occur, the A/D conversion result is not stored in the ADCR register.
<R>
<R>
<R>