Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  11   A/D  CONVERTER 

R01UH0305EJ0200  Rev.2.00 

 

 

392  

Jul 04, 2013 

If the A/D conversion result value is outside the range of values specified by the A/D conversion result comparison 

function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request 

signal (INTAD) is not generated. 

 

•  While in the select mode 

If the A/D conversion end interrupt request signal (INTAD) is not generated after A/D conversion ends, the clock 

request signal (an internal signal) is automatically set to the low level, and supplying the high-speed on-chip 

oscillator clock stops.  If a hardware trigger is input later, A/D conversion work is again performed in the SNOOZE 

mode. 

 

•  While in the scan mode 

If the A/D conversion end interrupt request signal (INTAD) is not generated even once during A/D conversion of the 

four channels, the clock request signal (an internal signal) is automatically set to the low level after A/D conversion 

of the four channels ends, and supplying the high-speed on-chip oscillator clock stops.  If a hardware trigger is input 

later, A/D conversion work is again performed in the SNOOZE mode. 

 

 

ADCS

Interrupt signal

(INTAD)

INTRTC

Clock request signal

(internal signal)

Conversion

channels

Channel 

1

Channel 

2

Channel 

3

Channel 

4

No interrupt is generated when 

conversion ends for any channel.

The clock request signal 

is set to the low level.