Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  12   SERIAL  ARRAY  UNIT 

R01UH0305EJ0200  Rev.2.00 

 

 

405  

Jul 04, 2013 

Figure 12-1 shows the block diagram of the serial array unit 0. 

 

 

Comm

unication

status

Serial data input pin

(when CSI01: SI01)

(when IIC01: SDA01)

Serial transfer end interrupt
(when CSI01: INTCSI01)
(when IIC01: INTIIC01)
(when UART0: INTSR0)

Serial clock select register 0 (SPS0)

PRS

013

4

PRS

003

PRS

012

PRS

011

PRS

010

PRS

002

PRS

001

PRS

000

4

f

CLK

f

CLK

/2

0

 to f

CLK

/2

15

Selector

f

CLK

/2

0

 to f

CLK

/2

15

Selector

CKS00

MD001

CCS00 STS00 MD002

Mode selection
CSI00 or IIC00

or UART0

(for transmission)

Edge

detection

Communication controller

Shift register

Serial data register 00 (SDR00)

Interrupt

controller

Edge/

level

detection

SOE03 SOE02 SOE01 SOE00

Serial output 
enable register 0 
(SOE0)

Serial clock I/O pin

(when CSI00: SCK00)

(when IIC00: SCL00)

PM10

SAU0EN

Peripheral enable
register 0 (PER0)

Serial data input pin

(when CSI00: SI00)

(when IIC00: SDA00)

(when UART0: R

X

D0)

Serial data output pin
(when CSI00: SO00)
(when IIC00: SDA00)
(when UART0: T

X

D0)

Serial mode register 00 (SMR00)

SE03

SE02

SE01

SE00

Serial channel 
enable status 
register 0 (SE0)

ST03

ST02

ST01

ST00

Serial channel 
stop register 0 
(ST0)

SS03

SS02

SS01

SS00

Serial channel 
start register 0 
(SS0)

(Buffer register block)

(Clock division setting block)

Error controller

TXE

00

RXE

00

DAP

00

CKP

00

Serial communication operation setting register 00 (SCR00)

EOC

00

PECT

00

Serial flag clear trigger 
register 00 (SIR00)

OVCT

00

PTC

001

SLC

000

PTC

000

DIR

00

SLC

001

DLS

001

DLS

000

TSF

00

OVF

00

BFF

00

PEF

00

Serial status register 00 (SSR00)

Output

controller

Serial transfer end interrupt
(when CSI00: INTCSI00)
(when IIC00: INTIIC00)
(when UART0: INTST0)

Clear

Channel 0

Mode selection
CSI01 or IIC01

or UART0

(for reception)

Communication controller

Channel 1

Serial data input pin

(when CSI10: SI10)

(when IIC10: SDA10)

(when UART1: R

X

D1)

Serial data output pin
(when CSI10: SO10)
(when IIC10: SDA10)
(when UART1: T

X

D1)

Serial transfer end interrupt
(when CSI10: INTCSI10)
(when IIC10: INTIIC10)
(when UART1: INTST1)

Mode selection
CSI10 or IIC10

or UART1

(for transmission)

Communication controller

Channel 2

Communication controller

Channel 3

CK01

CK00

f

MCK

f

TCLK

f

SCK

Prescaler

Output latch

(P10)

Serial clock I/O pin

(when CSI10: SCK10)

(when IIC10: SCL10)

Serial transfer error interrupt
(INTSRE0)

Serial data output pin
(when CSI01: SO01)
(when IIC01: SDA01)

Serial clock I/O pin

(when CSI01: SCK01)

(when IIC01: SCL01)

Serial clock I/O pin

(when CSI11: SCK11)

(when IIC11: SCL11)

CK01

CK00

CK01

CK00

CK01

CK00

SNFEN

10

Noise filter enable 
register 0 (NFEN0)

SNFEN

00

SSEC0

Serial standby 
control register 0 
(SSC0)

SWC0

Noise

elimination

enabled/

disabled

SNFEN00

Edge/level

detection

Selector

When UART0

When UART1

Serial data input pin

(when CSI11: SI11)

(when IIC11: SDA11)

Selector

Edge/level

detection

Edge/level

detection

Noise

elimination

enabled/

disabled

SNFEN10

PM11 or PM12

Output latch

(P11 or P12)

0

SOL02

0

SOL00

Serial output level 
register 0 (SOL0)

Error 

controller

Error 

controller

Serial transfer end interrupt
(when CSI11: INTCSI11)
(when IIC11: INTIIC11)
(when UART1: INTSR1)

Serial transfer error interrupt
(INTSRE1)

Serial data output pin
(when CSI11: SO11)
(when IIC11: SDA11)

Serial output register 0 (SO0)

CKO03

SO03

CKO02 CKO01 CKO00

SO02 SO01

SO00

0

0

0

0

0

0

0

0

Synchro-

nous

circuit

Synchro-

nous

circuit

Synchro-

nous

circuit

Synchro-

nous

circuit

Synchro-

nous

circuit

Mode selection
CSI11 or IIC11

or UART1

(for reception)

Error

information

Selector

Cloc

k controller

Selector

 

<R>