Renesas rl78 User Manual
RL78/G1A
CHAPTER 12 SERIAL ARRAY UNIT
R01UH0305EJ0200 Rev.2.00
406
Jul 04, 2013
Figure 12-2 shows the block diagram of the serial array unit 1.
Figure 12-2. Block Diagram of Serial Array Unit 1
Serial clock select register 1 (SPS1)
PRS
113
4
PRS
103
PRS
112
PRS
111
PRS
110
PRS
102
PRS
101
PRS
100
4
f
CLK
f
CLK
/2
0
to f
CLK
/2
15
Selector
f
CLK
/2
0
to f
CLK
/2
15
Selector
CKS10
MD101
CCS10 MD102
Communication controller
Shift register
Serial data register 10 (SDR10)
Interrupt
controller
Serial output register 1 (SO1)
SAU1EN
Peripheral enable
register 0 (PER0)
register 0 (PER0)
Serial mode register 10 (SMR10)
(Buffer register block)
(Clock division setting block)
Error controller
TXE
10
RXE
10
DAP
10
CKP
10
Serial communication operation setting register 10 (SCR10)
EOC
10
PECT
10
Serial flag clear trigger
register 10 (SIR10)
register 10 (SIR10)
OVCT
10
PTC
101
SLC
100
PTC
100
DIR
10
SLC
101
DLS
101
TSF
10
OVF
10
BFF
10
PEF
10
Serial status register 10 (SSR10)
Output
controller
Error
information
Clear
Channel 0
(LIN-bus supported)
CK11
CK10
f
MCK
f
TCLK
Prescaler
Noise
elimination
enabled/
disabled
SNFEN20
PM14 or PM13
Output latch
(P14 or P13)
(P14 or P13)
SOE11 SOE10
Serial output
enable register 1
(SOE1)
enable register 1
(SOE1)
SE11
SE10
Serial channel
enable status
register 1 (SE1)
enable status
register 1 (SE1)
ST11
ST10
Serial channel
stop register 1
(ST1)
stop register 1
(ST1)
SS11
SS10
Serial channel
start register 1
(SS1)
start register 1
(SS1)
0
SOL10
Serial output
level register 1
(SOL1)
level register 1
(SOL1)
CKO11 CKO10
SO11
SO10
0
0
0
0
0
0
0
0
Serial data output pin
(when CSI20: SO20)
(when IIC20: SDA20)
(when UART2: T
(when CSI20: SO20)
(when IIC20: SDA20)
(when UART2: T
X
D2)
Serial transfer end interrupt
(when CSI20: INTCSI20)
(when IIC20: INTIIC20)
(when UART2: INTST2)
(when CSI20: INTCSI20)
(when IIC20: INTIIC20)
(when UART2: INTST2)
PM15
Output latch
(P15)
Edge/
level
detection
Serial clock I/O pin
(when CSI20: SCK20)
(when IIC20: SCL20)
Serial data input pin
(when CSI20: SI20)
(when IIC20: SDA20)
(when UART2: R
X
D2)
Edge
detection
Synchro-
nous
circuit
Synchro-
nous
circuit
f
SCK
Mode selection
CSI20 or IIC20
CSI20 or IIC20
or UART2
(for transmission)
Communication controller
Channel 1
(LIN-bus supported)
Serial transfer error interrupt
(INTSRE2)
(INTSRE2)
CK11
CK10
When UART2
Error
controller
Mode selection
CSI21 or IIC21
CSI21 or IIC21
or UART2
(for reception)
Serial data input pin
(when CSI21: SI21)
(when IIC21: SDA21)
Serial clock I/O pin
(when CSI21: SCK21)
(when IIC21: SCL21)
Selector
Synchro-
nous
circuit
Edge/level
detection
Serial transfer end interrupt
(when CSI21: INTCSI21)
(when IIC21: INTIIC21)
(when UART2: INTSR2)
(when CSI21: INTCSI21)
(when IIC21: INTIIC21)
(when UART2: INTSR2)
Serial data output pin
(when CSI21: SO21)
(when IIC21: SDA21)
(when CSI21: SO21)
(when IIC21: SDA21)
Noise filter enable
register 0 (NFEN0)
SNFEN
20
0
0
0
0
0
0
0
0
0
0
1
1
1
1
DLS
100
Selector
Cloc
k controller
Selector
Comm
unication
status
<R>