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Renesas rl78 User Manual

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RL78/G1A 
 
CHAPTER  12   SERIAL  ARRAY  UNIT 
R01UH0305EJ0200  Rev.2.00 
 
 
428  
Jul 04, 2013 
12.3.14  Serial standby control register 0 (SSC0) 
The SSC0 register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when 
receiving CSI00 or UART0 serial data. 
The SSC0 register can be set by a 16-bit memory manipulation instruction. 
The lower 8 bits of the SSC0 register can be set with an 8-bit memory manipulation instruction with SSC0L. 
Reset signal generation clears the SSC0 register to 0000H. 
 
Caution  The maximum transfer rate in the SNOOZE mode is as follows. 
•  When using CSI00:  Until 1 Mbps 
•  When using UART0:  4800 bps only 
 
Figure 12-18.  Format of Serial Standby Control Register 0 (SSC0) 
 
Address: F0138H (SSC0)     After reset: 0000H     R/W 
Symbol 15 
14 
13
12 
11 
10
9 8 7 6 5 4 3 2 1 0 
SSC0  0 0 0 0 0 0 0 0 0 0 0 0 0 0 
SSEC
0 
SWC
0 
 
SSEC
0 
Selection of whether to enable or stop the generation of communication error interrupts in the SNOOZE 
mode 
0 
Enable the generation of error interrupts (INTSRE0). 
1 
Stop the generation of error interrupts (INTSRE0). 
•  The SSEC0 bit can be set to 1 or 0 only when both the SWC0 and EOC0n bits are set to 1 during UART reception 
in the SNOOZE mode. In other cases, clear the SSEC0 bit to 0. 
•  Setting SSEC0, SWC0 = 1, 0 is prohibited. 
 
SWC
0 
Setting of the SNOOZE mode 
0 
Do not use the SNOOZE mode function. 
1 
Use the SNOOZE mode function. 
•  When there is a hardware trigger signal in the STOP mode, the STOP mode is exited, and A/D conversion is 
performed without operating the CPU (the SNOOZE mode). 
•  The SNOOZE mode function can only be specified when the high-speed on-chip oscillator clock is selected for 
the CPU/peripheral hardware clock (f
CLK
).  If any other clock is selected, specifying this mode is prohibited. 
• Even when using SNOOZE mode, be sure to set the SWC0 bit to 0 in normal operation mode and change it to 1 
just before shifting to STOP mode. 
Also, be sure to change the SWC0 bit to 0 after returning from STOP mode to normal operation mode. 
 
Figure 12-19.  Interrupt Using the UART Reception with SNOOZE Mode 
EOC0n Bit 
SSEC0 Bit 
Normal Reception 
Reception Error 
0 
0 
INTSR0 is generated.
INTSR0 is generated. 
0 
1 
INTSR0 is generated.
INTSR0 is generated. 
1 
0 
INTSR0 is generated.
INTSRE0 is generated. 
1 
1 
INTSR0 is generated.
No interrupt is generated. 
 
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