Renesas rl78 User Manual

Page of 1004
 
RL78/G1A 
 
CHAPTER  12   SERIAL  ARRAY  UNIT 
R01UH0305EJ0200  Rev.2.00 
 
 
465  
Jul 04, 2013 
(4)  Processing flow (in continuous transmission/reception mode) 
 
Figure 12-46.  Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) 
(Type 1: DAPmn = 0, CKPmn = 0) 
 
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
INTCSIp
TSFmn
SOp pin
BFFmn
<1>
Note 1
MDmn0
STmn
 
Transmit data 1
Transmit data 2
Transmit data 3
Receive data 1
Receive data 2
Receive data 3
Receive data 1
Receive data 2
Receive data 3
Transmit data 1
Transmit data 2
Transmit data 3
Reception & shift operation
Reception & shift operation
Reception & shift operation
Data transmission/reception
Data transmission/reception
Data transmission/reception
    Write
   Write
    Write
Read
Read
Read
<8>
<2>
<2>
<2>
<3>
<2>
<2>
<4>
<4>
<5>
<6> <7>
Note 2
Note 2
Shift
register mn
 
 
Notes 1. If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn 
(SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten. 
 2. The transmit data can be read by reading the SDRmn register during this period.  At this time, the 
transfer operation is not affected. 
 
Caution  The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation.  
 
However, rewrite it before transfer of the last bit is started, so that it has been rewritten before the 
transfer end interrupt of the last transmit data. 
 
Remarks 1.  <1> to <8> in the figure correspond to <1> to <8> in Figure 12-47  Flowchart of Master 
Transmission/Reception (in Continuous Transmission/Reception  Mode). 
 2.  m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21), 
mn = 00 to 03, 10, 11 
 
<R> 
<R>