Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  12   SERIAL  ARRAY  UNIT 

R01UH0305EJ0200  Rev.2.00 

 

 

538  

Jul 04, 2013 

Of UART reception, UART2 of the 32, 48, and 64-pin products support LIN communication. 

For LIN reception, channel 1 of unit 1 is used. 

 

UART UART0 

UART1 

UART2 

Support of LIN communication

Not supported 

Not supported 

Supported 

Target channel 

− 

− 

Channel 1 of SAU1 

Pins used 

− 

− 

RxD2 

− 

− 

INTSR2 

Interrupt 

Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.) 

Error interrupt 

− 

− 

INTSRE2 

Error detection flag 

•  Framing error detection flag (FEF11) 
•  Parity error detection flag (PEF11) 
•  Overrun error detection flag (OVF11) 

Transfer data length 

8 bits 

Transfer rate

 Max. 

f

MCK

/6 [bps] (SDR11 [15:9] = 2 or more), Min. f

CLK

/(2 

× 2

15

 

× 128) [bps]  

Data phase 

Non-reverse output (default: high level) 

Reverse output (default: low level) 

Parity bit 

No parity bit (The parity bit is not checked.) 

Stop bit 

Check the first bit 

Data direction 

LSB first 

Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in 

the electrical specifications (see CHAPTER 29  ELECTRICAL SPECIFICATIONS (T

−40 to +85°C), 

−40 to +105°C)). 

 

Remark 

f

MCK

:  Operation clock frequency of target channel 

 

f

CLK

:  System clock frequency 

 

Figure 12-99 outlines a reception operation of LIN.