Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  12   SERIAL  ARRAY  UNIT 

R01UH0305EJ0200  Rev.2.00 

 

 

562  

Jul 04, 2013 

After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released. 

 

 

 

Stop condition

STmn

SEmn

SOEmn

SCLr output

SDAr output

Operation

stop

SOmn
bit manipulation

CKOmn
bit manipulation

SOmn
bit manipulation

 

 

Note  During a receive operation, the SOEmn bit of serial output enable register m (SOEm) is cleared to 0 before 

receiving the last data. 

 

 

 

m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21),  

mn = 00 to 03, 10, 11 

Starting generation of stop condition. 

End of IIC communication

Writing 1 to the STmn bit to clear 

(the SEmn bit is cleared to 0) 

Writing 0 to the SOEmn bit  

Writing 1 to the SOmn bit 

Writing 1 to the CKOmn bit 

Writing 0 to the SOmn bit 

Completion of data 

transmission/data reception

Wait 

Secure a wait time so that the specifications of 

I

2

C on the slave side are satisfied. 

Operation stop status (operable CKOmn 
manipulation) 

Operation disable status (operable SOmn 
manipulation) 

Timing to satisfy the low width standard of SCL 

for the I

2

C bus.