Renesas rl78 User Manual
RL78/G1A
CHAPTER 12 SERIAL ARRAY UNIT
R01UH0305EJ0200 Rev.2.00
564
Jul 04, 2013
Table 12-5. Selection of Operation Clock For Simplified I
2
C
SMRmn
Register
SPSm Register
Operation Clock (f
MCK
)
Note
CKSmn PRS
m13
PRS
m12
PRS
m11
PRS
m10
PRS
m03
PRS
m02
PRS
m01
PRS
m00
f
CLK
= 32 MHz
X X X X 0 0 0 0 f
CLK
32
MHz
X X X X 0 0 0 1 f
CLK
/2 16
MHz
X X X X 0 0 1 0 f
CLK
/2
2
8
MHz
X X X X 0 0 1 1 f
CLK
/2
3
4
MHz
X X X X 0 1 0 0 f
CLK
/2
4
2
MHz
X X X X 0 1 0 1 f
CLK
/2
5
1
MHz
X X X X 0 1 1 0 f
CLK
/2
6
500
kHz
X X X X 0 1 1 1 f
CLK
/2
7
250
kHz
X X X X 1 0 0 0 f
CLK
/2
8
125
kHz
X X X X 1 0 0 1 f
CLK
/2
9
62.5
kHz
X X X X 1 0 1 0 f
CLK
/2
10
31.25
kHz
0
X X X X 1 0 1 1 f
CLK
/2
11
15.63
kHz
0 0 0 0 X X X X
f
CLK
32
MHz
0 0 0 1 X X X X
f
CLK
/2 16
MHz
0 0 1 0 X X X X
f
CLK
/2
2
8
MHz
0 0 1 1 X X X X
f
CLK
/2
3
4
MHz
0 1 0 0 X X X X
f
CLK
/2
4
2
MHz
0 1 0 1 X X X X
f
CLK
/2
5
1
MHz
0 1 1 0 X X X X
f
CLK
/2
6
500
kHz
0 1 1 1 X X X X
f
CLK
/2
7
250
kHz
1 0 0 0 X X X X
f
CLK
/2
8
125
kHz
1 0 0 1 X X X X
f
CLK
/2
9
62.5
kHz
1 0 1 0 X X X X
f
CLK
/2
10
31.25
kHz
1
1 0 1 1 X X X X
f
CLK
/2
11
15.63
kHz
Other than above
Setting prohibited
Note When changing the clock selected for f
CLK
(by changing the system clock control register (CKC) value), do so
after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit
(SAU).
Remarks 1. X: Don’t care
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10, 11
Here is an example of setting an I
2
C transfer rate where f
MCK
= f
CLK
= 32 MHz.
f
CLK
= 32 MHz
I
2
C Transfer Mode
(Desired Transfer Rate)
Operation Clock (f
MCK
) SDRmn[15:9]
Calculated
Transfer Rate
Error from Desired Transfer
Rate
100 kHz
f
CLK
/2 79
100
kHz
0.0%
400 kHz
f
CLK
41
380
kHz
5.0%
Note
1 MHz
f
CLK
18
0.84
MHz
16.0%
Note
Note The error cannot be set to about 0% because the duty ratio of the SCL signal is 50%.