Renesas rl78 User Manual
RL78/G1A
CHAPTER 13 SERIAL INTERFACE IICA
Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (1/4)
Address: F0230H
After reset: 00H
R/W
Symbol
<7> <6> <5> <4> <3> <2> <1> <0>
IICCTL00 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0
STT0 SPT0
I
2
C operation enable
IICE0
Stop operation. Reset the IICA status register 0 (IICS0)
Note 1
. Stop internal operation.
0
1 Enable
operation.
Be sure to set this bit (1) while the SCLA0 and SDAA0 lines are at high level.
Condition for clearing (IICE0 = 0)
Condition for setting (IICE0 = 1)
• Cleared by instruction
• Set by instruction
• Reset
LREL0
Notes 2, 3
Exit
from
communications
0 Normal
operation
1
This exits from the current communications and sets standby mode. This setting is automatically cleared
to 0 after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCLA0 and SDAA0 lines are set to high impedance.
The following flags of IICA control register 00 (IICCTL00) and the IICA status register 0 (IICS0) are
cleared to 0.
• STT0 • SPT0 • MSTS0 • EXC0 • COI0 • TRC0 • ACKD0 • STD0
The standby mode following exit from communications remains in effect until the following communications entry
conditions are met.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL0 = 0)
Condition for setting (LREL0 = 1)
• Automatically cleared after execution
• Set by instruction
• Reset
WREL0
Notes 2, 3
Wait
cancellation
0
Do not cancel wait
1
Cancel wait. This setting is automatically cleared after wait is canceled.
When the WREL0 bit is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status
(TRC0 = 1), the SDAA0 line goes into the high impedance state (TRC0 = 0).
Condition for clearing (WREL0 = 0)
Condition for setting (WREL0 = 1)
• Automatically cleared after execution
• Set by instruction
• Reset
Notes 1. The IICA status register 0 (IICS0), the STCF and IICBSY bits of the IICA flag register 0 (IICF0), and
the CLD0 and DAD0 bits of IICA control register 01 (IICCTL01) are reset.
2. The signal of this bit is invalid while IICE0 is 0.
3. When the LREL0 and WREL0 bits are read, 0 is always read.
Caution If the operation of I
2
C is enabled (IICE0 = 1) when the SCLA0 line is high level, the SDAA0 line
is low level, and the digital filter is turned on (DFC0 bit of IICCTL01 register = 1), a start
condition will be inadvertently detected immediately. In this case, set (1) the LREL0 bit by
using a 1-bit memory manipulation instruction immediately after enabling operation of I
2
C
(IICE0 = 1).
R01UH0305EJ0200 Rev.2.00
574
Jul 04, 2013