Renesas rl78 User Manual
RL78/G1A
CHAPTER 13 SERIAL INTERFACE IICA
Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (3/4)
STT0
Notes 1, 2
Start condition trigger
0
Do not generate a start condition.
1
When bus is released (in standby state, when IICBSY = 0):
If this bit is set (1), a start condition is generated (startup as the master).
When a third party is communicating:
• When communication reservation function is enabled (IICRSV = 0)
Functions as the start condition reservation flag. When set to 1, automatically generates a start
Functions as the start condition reservation flag. When set to 1, automatically generates a start
condition after the bus is released.
• When communication reservation function is disabled (IICRSV = 1)
Even if this bit is set (1), the STT0 bit is cleared and the STT0 clear flag (STCF) is set (1). No start
Even if this bit is set (1), the STT0 bit is cleared and the STT0 clear flag (STCF) is set (1). No start
condition is generated.
In the wait state (when master device):
Generates a restart condition after releasing the wait.
Cautions concerning set timing
• For master reception:
• For master reception:
Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when the
ACKE0 bit has been cleared to 0 and slave has been notified of final reception.
• For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1
during the wait period that follows output of the ninth clock.
• Cannot be set to 1 at the same time as stop condition trigger (SPT0).
• Once STT0 is set (1), setting it again (1) before the clear condition is met is not allowed.
• Once STT0 is set (1), setting it again (1) before the clear condition is met is not allowed.
Condition for clearing (STT0 = 0)
Condition for setting (STT0 = 1)
• Cleared by setting the STT0 bit to 1 while
communication reservation is prohibited.
• Set by instruction
• Cleared by loss in arbitration
• Cleared after start condition is generated by master
• Cleared after start condition is generated by master
device
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
• When IICE0 = 0 (operation stop)
• Reset
Notes 1. The signal of this bit is invalid while IICE0 is 0.
2. The STT0 bit is always read as 0.
<R>
Remark IICRSV: Bit 0 of IIC flag register 0 (IICF0)
STCF: Bit 7 of IIC flag register 0 (IICF0)
R01UH0305EJ0200 Rev.2.00
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Jul 04, 2013