Renesas rl78 User Manual
RL78/G1A
CHAPTER 13 SERIAL INTERFACE IICA
Cautions 1. The fastest operation frequency of the IICA operation clock (f
MCK
) is 20 MHz (Max.).
Set the bit 0 (PRS0) of the IICA control register 01 (IICCTL01) to 1, only when the f
CLK
exceeds
20 MHz.
2. Note the minimum f
CLK
operation frequency when setting the transfer clock.
The minimum f
CLK
operation frequency for serial interface IICA is determined according to the
mode.
Fast mode:
f
CLK
= 3.5 MHz (MIN.)
Fast mode plus: f
CLK
= 10 MHz (MIN.)
Normal mode: f
CLK
= 1 MHz (MIN.)
Remarks 1. Calculate the rise time (t
R
) and fall time (t
F
) of the SDAA0 and SCLA0 signals separately, because
they differ depending on the pull-up resistance and wire load.
2. IICWL0: IICA low-level width setting register 0
IICWH0: IICA high-level width setting register 0
t
F
:
SDAA0 and SCLA0 signal falling times
t
R
:
SDAA0 and SCLA0 signal rising times
f
MCK
:
IICA operation clock frequency
<R>
R01UH0305EJ0200 Rev.2.00
589
Jul 04, 2013