Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  13   SERIAL  INTERFACE  IICA 

The I

2

C usually cancels a wait state by the following processing. 

 

•  Writing data to the IICA shift register 0 (IICA0) 
•  Setting bit 5 (WREL0) of IICA control register 00 (IICCTL00) (canceling wait) 
•  Setting bit 1 (STT0) of the IICCTL00 register (generating start condition)

 

•  Setting bit 0 (SPT0) of the IICCTL00 register (generating stop condition)

 

 

Note Master 

only 

 

When the above wait canceling processing is executed, the I

2

C cancels the wait state and communication is resumed. 

To cancel a wait state and transmit data (including addresses), write the data to the IICA0 register. 

To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL0) of the IICCTL00 

register to 1. 

To generate a restart condition after canceling a wait state, set bit 1 (STT0) of the IICCTL00 register to 1. 

To generate a stop condition after canceling a wait state, set bit 0 (SPT0) of the IICCTL00 register to 1. 

Execute the canceling processing only once for one wait state. 

If, for example, data is written to the IICA0 register after canceling a wait state by setting the WREL0 bit to 1, an 

incorrect value may be output to SDAA0 line because the timing for changing the SDAA0 line conflicts with the timing for 

writing the IICA0 register. 

In addition to the above, communication is stopped if the IICE0 bit is cleared to 0 when communication has been 

aborted, so that the wait state can be canceled. 

If the I

2

C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL0) of the 

IICCTL00 register, so that the wait state can be canceled. 

 

 

R01UH0305EJ0200  Rev.2.00 

 

 

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Jul 04, 2013