Renesas rl78 User Manual

Page of 1004
 
RL78/G1A 
 
CHAPTER  13   SERIAL  INTERFACE  IICA 
13.5.12  Arbitration 
When several master devices simultaneously generate a start condition (when the STT0 bit is set to 1 before the STD0 
bit is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data 
differs.  This kind of operation is called arbitration. 
When one of the master devices loses in arbitration, an arbitration loss flag (ALD0) in the IICA status register 0 (IICS0) 
is set (1) via the timing by which the arbitration loss occurred, and the SCLA0 and SDAA0 lines are both set to high 
impedance, which releases the bus. 
The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop 
condition is detected, etc.) and the ALD0 = 1 setting that has been made by software. 
For details of interrupt request timing, see 13.5.8  Interrupt request (INTIICA0) generation timing and wait control
 
Remark   STD0:  Bit 1 of IICA status register 0 (IICS0) 
 
STT0:   Bit 1 of IICA control register 00 (IICCTL00) 
 
Figure 13-21.  Arbitration Timing Example 
 
SCLA0
SDAA0
SCLA0
SDAA0
SCLA0
SDAA0
Hi-Z
Hi-Z
Master 1 loses arbitration
Master 1
Master 2
Transfer lines
 
 
R01UH0305EJ0200  Rev.2.00 
 
 
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Jul 04, 2013