Renesas rl78 User Manual

RL78/G1A

CHAPTER 13 SERIAL INTERFACE IICA

The meanings of <8> to <19> in (3) Data ~ data ~ stop condition in Figure 13-33 are explained below.

<8> The master device sets a wait status (SCLA0 = 0) at the falling edge of the 8th clock, and issues an

interrupt (INTIICA0: end of transfer). Because of ACKE0 = 0 in the master device, the master device then

sends an ACK by hardware to the slave device.

<9> The master device reads the received data and releases the wait status (WREL0 = 1).

<10> The ACK is detected by the slave device (ACKD0 = 1) at the rising edge of the 9th clock.

<11> The slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and the slave device

issue an interrupt (INTIICA0: end of transfer).

<12> By the slave device writing the data to transmit to the IICA register, the wait status set by the slave device is

released. The slave device then starts transferring data to the master device.

<13> The master device issues an interrupt (INTIICA0: end of transfer) at the falling edge of the 8th clock, and

sets a wait status (SCLA0 = 0). Because ACK control (ACKE0 = 1) is performed, the bus data line is at the

low level (SDAA0 = 0) at this stage.

<14> The master device sets NACK as the response (ACKE0 = 0) and changes the timing at which it sets the

wait status to the 9th clock (WTIM0 = 1).

<15> If the master device releases the wait status (WREL0 = 1), the slave device detects the NACK (ACK = 0) at

the rising edge of the 9th clock.

<16> The master device and slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and

both the master device and slave device issue an interrupt (INTIICA0: end of transfer).

<17> When the master device issues a stop condition (SPT0 = 1), the bus data line is cleared (SDAA0 = 0) and

the master device releases the wait status. The master device then waits until the bus clock line is set

(SCLA0 = 1).

<18> The slave device acknowledges the NACK, halts transmission, and releases the wait status (WREL0 = 1) to

end communication. Once the slave device releases the wait status, the bus clock line is set (SCLA0 = 1).

<19> Once the master device recognizes that the bus clock line is set (SCLA0 = 1) and after the stop condition

setup time has elapsed, the master device sets the bus data line (SDAA0 = 1) and issues a stop condition

(i.e. SCLA0 =1 changes SDAA0 from 0 to 1). The slave device detects the generated stop condition and

slave device issue an interrupt (INTIICA0: stop condition).

Remark <1> to <19> in Figure 13-33 represent the entire procedure for communicating data using the I

C bus.

Figure 13-33 (1) Start condition ~ address ~ data shows the processing from <1> to <7>, Figure 13-33

(2) Address ~ data ~ data shows the processing from <3> to <12>, and Figure 13-33 (3) Data ~ data ~

stop condition shows the processing from <8> to <19>.

R01UH0305EJ0200 Rev.2.00

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Jul 04, 2013