Renesas rl78 User Manual

 

RL78/G1A 

CHAPTER  14   MULTIPLIER  AND  DIVIDER/MULTIPLY-ACCUMULATOR 

The register configuration differs between when multiplication is executed and when division is executed, as follows. 

 

•  Register configuration during multiplication 

       <Multiplier A>       <Multiplier B>                                     <Product> 

MDAL (bits 15 to 0) 

× MDAH (bits 15 to 0) = [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] 

 

•  Register configuration during multiply-accumulation 

       <Multiplier A>         <Multiplier B>       < accumulated value >               < accumulated result > 

MDAL (bits 15 to 0) 

× MDAH (bits 15 to 0) + MDC (bits 31 to 0) = [MDCH (bits 15 to 0), MDCL (bits 15 to 0)] 

(The multiplication result is stored in the MDBH (bits 15 to 0) and MDBL (bits 15 to 0).) 

 

•  Register configuration during division 

                         <Dividend>                                               <Divisor> 

[MDAH (bits 15 to 0), MDAL (bits 15 to 0)] 

÷ [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] = 

                          <Quotient>                                            <Remainder> 

[MDAH (bits 15 to 0), MDAL (bits 15 to 0)] 

⋅⋅⋅ [MDCH (bits 15 to 0), MDCL (bits 15 to 0)] 

 

R01UH0305EJ0200  Rev.2.00 

 

 

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Jul 04, 2013