Renesas rl78 User Manual

 

RL78/G1A 

CHAPTER  14   MULTIPLIER  AND  DIVIDER/MULTIPLY-ACCUMULATOR 

 

• Initial setting 

<1>  Set the multiplication/division control register (MDUC) to 48H. 

<2>  Set the initial accumulated value of higher 16 bits to multiplication/division data register C (H) (MDCH). 

 

(<3>  If the accumulated value in the MDCH register is negative, the MACSF bit is set to 1.) 

<4>  Set the initial accumulated value of lower 16 bits to multiplication/division data register C (L) (MDCL). 

<5>  Set the multiplicand to multiplication/division data register A (L) (MDAL). 

<6>  Set the multiplier to multiplication/division data register A (H) (MDAH). 

 

(There is no preference in the order of executing steps <2>, <4>, and <5>.  Multiplication operation is 

automatically started when the multiplier is set to the MDAH register of <6>, respectively.) 

•  During operation processing 

<7> The 

multiplication 

operation finishes in one clock cycle. 

(The multiplication result is stored in multiplication/division data register B (L) (MDBL) and multiplication/division 

data register B (H) (MDBH).) 

<8>  After <7>, the multiply-accumulation operation finishes in one additional clock cycle.  (There is a wait of at least 

two clock cycles after specifying the initial settings is finished (<6>).) 

• Operation end 

<9>  If the accumulated value stored in the MDCL and MDCH registers is positive, the MACSF bit is cleared to 0. 

<10> Read the accumulated value (lower 16 bits) from the MDCL register. 

<11> Read the accumulated value (higher 16 bits) from the MDCH register. 

(There is no preference in the order of executing steps <10> and <11>.) 

(<12> If the result of the multiply-accumulation operation causes an overflow, the MACOF bit is set to 1, INTMD 

signal is occurred.) 

• Next operation 

<13> Start with the initial settings of each step to change the operation mode.  When the same operation mode is 

used sequentially, settings <1> to <5> can be omitted. 

Caution  The data is in the two’s complement format in multiply-accumulation (signed) operation. 

Remark  Steps <1> to <12> correspond to <1> to <12> in Figure 14-9. 

 

R01UH0305EJ0200  Rev.2.00 

 

 

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Jul 04, 2013