Renesas rl78 User Manual

RL78/G1A

CHAPTER 15 DMA CONTROLLER

15.2.2 DMA RAM address register n (DRAn)

This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA channel n.

Addresses of the internal RAM area other than the general-purpose registers (see Table 15-2) can be set to this

Set the lower 16 bits of the RAM address.

This register is automatically incremented when DMA transfer has been started. It is incremented by +1 in the 8-bit

transfer mode and by +2 in the 16-bit transfer mode. DMA transfer is started from the address set to this DRAn register.

When the data of the last address has been transferred, the DRAn register stops with the value of the last address +1 in

the 8-bit transfer mode, and the last address +2 in the 16-bit transfer mode.

In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address.

The DRAn register can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA transfer.

Reset signal generation clears this register to 0000H.

Figure 15-2. Format of DMA RAM Address Register n (DRAn)

Address: FFFB2H, FFFB3H (DRA0), FFFB4H, FFFB5H (DRA1) After reset: 0000H R/W

DRA0H: FFFB3H

DRA1H: FFFB5H

DRA0L: FFFB2H

DRA1L: FFFB4H

15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

DRAn

(n = 0, 1)

Table 15-2. Internal RAM Area other than the General-purpose Registers

Part Number

Internal RAM Area other than the General-purpose Registers

R5F10ExA (x = 8, B, G)

R5F10ExC (x = 8, B, G, L)

FF700H to FFEDFH

R5F10ExD (x = 8, B, G, L)

FF300H to FFEDFH

R5F10ExE (x = 8, B, G, L)

FEF00H to FFEDFH

Remark n: DMA channel number (n = 0, 1)

R01UH0305EJ0200 Rev.2.00

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Jul 04, 2013