Renesas rl78 User Manual
RL78/G1A
CHAPTER 15 DMA CONTROLLER
15.3.2 DMA operation control register n (DRCn)
The DRCn register is a register that is used to enable or disable transfer of DMA channel n.
Rewriting bit 7 (DENn) of this register is prohibited during operation (when DSTn = 1).
The DRCn register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 15-5. Format of DMA Operation Control Register n (DRCn)
Address: FFFBCH (DRC0), FFFBDH (DRC1) After reset: 00H R/W
Symbol
<7>
6 5 4 3 2 1
<0>
DRCn
DENn
0 0 0 0 0 0
DSTn
DENn
DMA operation enable flag
0
Disables operation of DMA channel n (stops operating cock of DMA).
1
Enables operation of DMA channel n.
DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1).
DSTn
DMA transfer mode flag
0
DMA transfer of DMA channel n is completed.
1
DMA transfer of DMA channel n is not completed (still under execution).
DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1).
When a software trigger (STGn) or the start source trigger set by the IFCn3 to IFCn0 bits is input, DMA transfer is
started.
When DMA transfer is completed after that, this bit is automatically cleared to 0.
Write 0 to this bit to forcibly terminate DMA transfer under execution.
Caution The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. When a DMA transfer is terminated
without waiting for generation of the interrupt (INTDMAn) of DMAn, therefore, set the DSTn bit
to 0 and then the DENn bit to 0 (for details, see 15.5.5 Forced termination by software).
Remark n: DMA channel number (n = 0, 1)
R01UH0305EJ0200 Rev.2.00
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Jul 04, 2013