Renesas rl78 User Manual

RL78/G1A

CHAPTER 16 INTERRUPT FUNCTIONS

Table 16-2. Flags Corresponding to Interrupt Request Sources (2/4)

Interrupt Request Flag

Interrupt Mask Flag

Priority Specification Flag

Interrupt

Source

64-pin

48-pin

32-pin

25-pin

INTST2

Note 1

STIF2

Note 1

STMK2

Note 1

STPR02,

STPR12

Note 1

√ √ √

−

INTCSI20

Note 1

CSIIF20

Note 1

CSIMK20

Note 1

CSIPR020, CSIPR120

Note 1

√ √ √

−

INTIIC20

Note 1

IICIF20

Note 1

IICMK20

Note 1

IICPR020, IICPR120

Note 1

√ √ √

−

INTSR2

Note 2

SRIF2

Note 2

SRMK2

Note 2

SRPR02,

SRPR12

Note 2

√ √ √

−

INTCSI21

Note 2

CSIIF21

Note 2

CSIMK21

Note 2

CSIPR021, CSIPR121

Note 2

√ √ −

−

INTIIC21

Note 2

IICIF21

Note 2

IICMK21

Note 2

IICPR021, IICPR121

Note 2

√ √ −

−

INTSRE2 SREIF2

SREMK2

SREPR02,

SREPR12

√ √ √

−

INTDMA0 DMAIF0

DMAMK0

DMAPR00,

DMAPR10

√ √ √

√

INTDMA1 DMAIF1

DMAMK1

DMAPR01,

DMAPR11

√ √ √

√

INTST0

Note 3

STIF0

Note 3

STMK0

Note 3

STPR00,

STPR10

Note 3

√ √ √

√

INTCSI00

Note 3

CSIIF00

Note 3

CSIMK00

Note 3

CSIPR000, CSIPR100

Note 3

√ √ √

√

INTIIC00

Note 3

IICIF00

Note 3

IICMK00

Note 3

IICPR000, IICPR100

Note 3

√ √ √

√

INTSR0

Note 4

SRIF0

Note 4

SRMK0

Note 4

SRPR00,

SRPR10

Note 4

√ √ √

√

INTCSI01

Note 4

CSIIF01

Note 4

CSIMK01

Note 4

CSIPR001, CSIPR101

Note 4

√ √ −

−

INTIIC01

Note 4

IICIF01

Note 4

IICMK01

Note 4

IICPR001, IICPR101

Note 4

√ √ −

−

INTSRE0

Note 5

SREIF0

Note 5

SREMK0

Note 5

SREPR00,

SREPR10

Note 5

√ √ √

√

INTTM01H

Note 5

TMIF01H

Note 5

IF0H

TMMK01H

Note 5

MK0H

TMPR001H,

TMPR101H

Note 5

PR00H,

PR10H

√ √ √

√

Notes 1. If one of the interrupt sources INTST2, INTCSI20, and INTIIC20 is generated, bit 0 of the IF0H register is set

to 1. Bit 0 of the MK0H, PR00H, and PR10H registers can be used for all three of these interrupt sources.

If one of the interrupt sources INTSR2, INTCSI21, and INTIIC21 is generated, bit 1 of the IF0H register is set

to 1. Bit 1 of the MK0H, PR00H, and PR10H registers can be used for all three of these interrupt sources.

If one of the interrupt sources INTST0, INTCSI00, and INTIIC00 is generated, bit 5 of the IF0H register is set

to 1. Bit 5 of the MK0H, PR00H, and PR10H registers can be used for all three of these interrupt sources.

If one of the interrupt sources INTSR0, INTCSI01, and INTIIC01 is generated, bit 6 of the IF0H register is set

to 1. Bit 6 of the MK0H, PR00H, and PR10H registers can be used for all three of these interrupt sources.

Do not use the error interrupt of UART0 reception and the interrupt of channel 1 of TAU0 (while the higher 8

bits are operating at a timer) at the same time because they share flags for the interrupt request sources. If

the error interrupt of UART0 reception is not used (EOC01 = 0), UART0 and channel 1 of TAU0 (while the

higher 8 bits are operating at a timer) can be used at the same time. If the interrupt source INTSRE0 or

INTTM01H is generated, bit 7 of the IF0H register is set to 1. Bit 7 of the MK0H, PR00H, and PR10H

registers can be used for both these interrupt sources.

R01UH0305EJ0200 Rev.2.00

695

Jul 04, 2013