Renesas rl78 User Manual

RL78/G1A

CHAPTER 16 INTERRUPT FUNCTIONS

Table 16-2. Flags Corresponding to Interrupt Request Sources (3/4)

Interrupt Request Flag

Interrupt Mask Flag

Priority Specification Flag

Interrupt

Source

64-pin

48-pin

32-pin

25-pin

INTST1

Note 1

STIF1

Note 1

STMK1

Note 1

STPR01,

STPR11

Note 1

√ √ √

√

INTCSI10

Note 1

CSIIF10

Note 1

CSIMK10

Note 1

CSIPR010, CSIPR110

Note 1

√ − −

−

INTIIC10

Note 1

IICIF10

Note 1

IICMK10

Note 1

IICPR010, IICPR110

Note 1

√ − −

−

INTSR1

Note 2

SRIF1

Note 2

SRMK1

Note 2

SRPR01,

SRPR11

Note 2

√ √ √

√

INTCSI11

Note 2

CSIIF11

Note 2

CSIMK11

Note 2

CSIPR011, CSIPR111

Note 2

√ √ √

√

INTIIC11

Note 2

IICIF11

Note 2

IICMK11

Note 2

IICPR011, IICPR111

Note 2

√ √ √

√

INTSRE1

Note 3

SREIF1

Note 3

SREMK1

Note 3

SREPR01,

SREPR11

Note 3

√ √ √

√

INTTM03H

Note 3

TMIF03H

Note 3

TMMK03H

Note 3

TMPR003H, TMPR103H

Note 3

√ √ √

√

INTIICA0 IICAIF0

IICAMK0

IICAPR00,

IICAPR10

√ √ √

√

INTTM00 TMIF00

TMMK00

TMPR000,

TMPR100

√ √ √

√

INTTM01 TMIF01

TMMK01

TMPR001,

TMPR101

√ √ √

√

INTTM02 TMIF02

TMMK02

TMPR002,

TMPR102

√ √ √

√

INTTM03 TMIF03

IF1L

TMMK03

MK1L

TMPR003, TMPR103

PR01L,

PR11L

√ √ √

√

INTAD ADIF

ADMK

ADPR0,

ADPR1

√ √ √

√

INTRTC RTCIF

RTCMK

RTCPR0,

RTCPR1

√ √ √

√

INTIT ITIF

ITMK

ITPR0,

ITPR1

√ √ √

√

INTKR KRIF

KRMK

KRPR0,

KRPR1

√ √ √ (√)

INTTM04 TMIF04

IF1H

TMMK04

MK1H

TMPR004, TMPR104

PR01H,

PR11H

√ √ √

√

Notes 1. If one of the interrupt sources INTST1, INTCSI10, and INTIIC10 is generated, bit 0 of the IF1L register is set

to 1. Bit 0 of the MK1L, PR01L, and PR11L registers can be used for all three of these interrupt sources.

If one of the interrupt sources INTSR1, INTCSI11, and INTIIC11 is generated, bit 1 of the IF1L register is set

to 1. Bit 1 of the MK1L, PR01L, and PR11L registers can be used for all three of these interrupt sources.

Do not use the error interrupt of UART1 reception and the interrupt of channel 3 of TAU0 (while the higher 8

bits are operating at a timer) at the same time because they share flags for the interrupt request sources. If

the error interrupt of UART1 reception is not used (EOC03 = 0), UART1 and channel 3 of TAU0 (while the

higher 8 bits are operating at a timer) can be used at the same time. If the interrupt source INTSRE1 or

INTTM03H is generated, bit 2 of the IF1L register is set to 1. Bit 2 of the MK1L, PR01L, and PR11L

registers can be used for both these interrupt sources.

<R>

R01UH0305EJ0200 Rev.2.00

696

Jul 04, 2013