Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  16   INTERRUPT  FUNCTIONS 

<R> 

The program status word is a register used to hold the instruction execution result and the current status for an interrupt 

request.  The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls multiple 

interrupt servicing are mapped to the PSW.  

Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated 

instructions (EI and DI).  When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the 

contents of the PSW are automatically saved into a stack and the IE flag is reset to 0.  If a maskable interrupt request is 

acknowledged, the contents of the priority specification flag register of the acknowledged interrupt are not 00, its value 

minus 1 is transferred to the ISP0 and ISP1 flags.  The PSW contents are also saved into the stack with the PUSH PSW 

instruction.  They are restored from the stack with the RETI, RETB, and POP PSW instructions.   

Reset signal generation sets PSW to 06H.   

 

 

<7>

IE

<6>

Z

<5>

RBS1

<4>

AC

<3>

RBS0

<2>

ISP1

<1>

ISP0

0

CY

PSW

After reset

06H

ISP1

0

0

1

1

Enables interrupt of level 0

(while interrupt of level 1 or 0 is being serviced).

Enables interrupt of level 0 and 1

(while interrupt of level 2 is being serviced).

Enables interrupt of level 0 to 2

(while interrupt of level 3 is being serviced).

Enables all interrupts

(waits for acknowledgment of an interrupt).

Jul 04, 2013 

IE

0

1

Disabled

Enabled

Priority of interrupt currently being serviced

Interrupt request acknowledgment enable/disable

Used when normal instruction is executed

ISP0

0

1

0

1

 

 

 

R01UH0305EJ0200  Rev.2.00 

 

 

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