Renesas rl78 User Manual
RL78/G1A
CHAPTER 17 KEY INTERRUPT FUNCTION
17.4.2 When using the key interrupt flag (KRMD = 1)
A key interrupt (INTKR) is generated when the valid edge specified by the setting of the KREG bit is input to a key
interrupt pin (KR0 to KR5). The channels to which the valid edge was input can be identified by reading the key return flag
register (KRF) after the key interrupt (INTKR) is generated.
If the KRMD bit is set to 1, the INTKR signal is cleared by clearing the corresponding bit in the KRF register.
As shown in Figure 17-9, only one interrupt is generated each time a falling edge is input to one channel (when KREG
= 0), regardless of whether the KRFn bit is cleared before or after a rising edge is input.
Figure 17-9. Basic Operation of the INTKR Signal When the Key Interrupt Flag Is Used
(When KRMD = 1 and KREG = 0)
(a) When KRF0 is cleared after a rising edge is input to the KR0 pin
KR0
KRF0
Cleared by
software
software
INTKR
KRIF
Note 1
Note 2
Delay
time
time
Clear
(b) When KRF0 is cleared before a rising edge is input to the KR0 pin
KR0
KRF0
INTKR
KRIF
Note 1
Note 2
Delay
time
time
Clear
Cleared by software
Notes 1. The maximum delay time is the maximum value of the high-level width and low-level width of the key
interrupt input (see 29.4 AC Characteristics and 30.4 AC Characteristics for details).
2. Acknowledgment of vectored interrupt request or bit cleared by software
R01UH0305EJ0200 Rev.2.00
723
Jul 04, 2013