Renesas rl78 User Manual
RL78/G1A
CHAPTER 18 STANDBY FUNCTION
Table 18-1. Operating Statuses in HALT Mode (1/2)
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock
HALT Mode Setting
Item
When CPU Is Operating on
High-speed On-chip Oscillator
Clock (f
IH
)
When CPU Is Operating on
X1 Clock (f
X
)
When CPU Is Operating on
External Main System Clock
(f
EX
)
System clock
Clock supply to the CPU is stopped
f
IH
Operation continues (cannot
be stopped)
be stopped)
Operation disabled
f
X
Operation continues (cannot
be stopped)
be stopped)
Cannot operate
Main system clock
f
EX
Operation disabled
Cannot operate
Operation continues (cannot
be stopped)
be stopped)
f
XT
Subsystem clock
f
EXS
Status before HALT mode was set is retained
f
IL
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of
subsystem clock supply mode control register (OSMC)
• WUTMMCK0 = 1: Oscillates
• WUTMMCK0 = 0 and WDTON = 0: Stops
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops
subsystem clock supply mode control register (OSMC)
• WUTMMCK0 = 1: Oscillates
• WUTMMCK0 = 0 and WDTON = 0: Stops
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops
CPU
Code flash memory
Data flash memory
RAM
Operation stopped
Port (latch)
Status before HALT mode was set is retained
Timer array unit
Real-time clock (RTC)
12-bit interval timer
Operable
Watchdog timer
See CHAPTER 10 WATCHDOG TIMER
Clock output/buzzer output
A/D converter
Serial array unit (SAU)
Serial interface (IICA)
Multiplier and divider/multiply-
accumulator
accumulator
DMA controller
Power-on-reset function
Voltage detection function
External interrupt
Key interrupt function
High-speed CRC
Operable
CRC
operation
function
operation
function
General-purpose
CRC
CRC
Operation stopped
RAM parity error detection
function
function
RAM guard function
SFR guard function
Illegal-memory access
detection function
detection function
Operation stopped
Remark Operation
stopped:
Operation is automatically stopped before switching to the HALT mode.
Operation disabled: Operation is stopped before switching to the HALT mode.
f
IH
:
High-speed on-chip oscillator clock
f
EX
:
External main system clock
f
IL
:
Low-speed on-chip oscillator clock
f
XT
: XT1
clock
f
X
: X1
clock
f
EXS
:
External subsystem clock
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Jul 04, 2013