Renesas rl78 User Manual
RL78/G1A
CHAPTER 18 STANDBY FUNCTION
Figure 18-3. STOP Mode Release by Interrupt Request Generation (2/2)
(2) When high-speed system clock (X1 oscillation) is used as CPU clock
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Normal operation
(high-speed
system clock)
Normal operation
(high-speed
system clock)
Oscillates
Oscillates
STOP
instruction
STOP mode
Standby release signal
Note 1
Oscillation stopped
High-speed
system clock
(X1 oscillation)
Status of CPU
Supply of the
clock is stopped
Interrupt
request
Wait
STOP mode release time
Note 2
Notes 1. For details of the standby release signal, see Figure 16-1.
2.
STOP mode release time
Supply of the clock is stopped: 18
μ
s to “whichever is longer 65
μ
s and the oscillation stabilization
time (set by OSTS)”
Wait
• When vectored interrupt servicing is carried out:
• When vectored interrupt servicing is carried out:
10 to 11 clocks
• When vectored interrupt servicing is not carried out: 4 to 5 clocks
(3) When high-speed system clock (external clock input) is used as CPU clock
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Interrupt
request
STOP
instruction
Standby release signal
Note 1
Status of CPU
High-speed
system clock
(external clock input)
Oscillates
Normal operation
(high-speed
system clock)
STOP mode
Oscillation stopped
Oscillates
Normal operation
(high-speed
system clock)
Wait
Supply of the
clock is stopped
STOP mode release time
Note 2
Notes 1.
For details of the standby release signal, see Figure 16-1.
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2.
STOP mode release time
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Supply of the clock is stopped: 18 to 65
μ
s
Wait
• When vectored interrupt servicing is carried out:
• When vectored interrupt servicing is carried out:
7 clocks
• When vectored interrupt servicing is not carried out: 1 clock
Caution To reduce the oscillation stabilization time after release from the STOP mode while CPU
operates based on the high-speed system clock (X1 oscillation), switch the clock to the high-
speed on-chip oscillator clock temporarily before executing the STOP instruction.
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Remarks 1. The period during which clock supply stops depends on the temperature conditions and the STOP
mode period.
2. The broken lines indicate the case when the interrupt request that has released the standby mode
is acknowledged.
R01UH0305EJ0200 Rev.2.00
735
Jul 04, 2013