Renesas rl78 User Manual

 

RL78/G1A 

CHAPTER  21   VOLTAGE  DETECTOR 

 

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Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the detection voltage (V

LVD

) by using the 

option byte 000C1H. 

 

The operation is started in the following initial setting state when the reset mode is set. 

•

 Bit 7 (LVISEN) of the voltage detection register (LVIM) is set to 0 (disable rewriting of voltage detection level 

register (LVIS)) 

•

  The initial value of the voltage detection level select register (LVIS) is set to 81H. 

Bit 7 (LVIMD) is 1 (reset mode). 

Bit 0 (LVILV) is 1 (voltage detection level: V

LVD

). 

 

• Operation in LVD reset mode 

In the reset mode (option byte LVIMDS1, LVIMDS0 = 1, 1), the state of an internal reset by LVD is retained until 

the supply voltage (V

DD

) exceeds the voltage detection level (V

LVD

) after power is supplied.  The internal reset is 

released when the supply voltage (V

DD

) exceeds the voltage detection level (V

LVD

). 

At the fall of the operating voltage, an internal reset by LVD is generated when the supply voltage (V

DD

) falls 

below the voltage detection level (V

LVD

). 

 

Figure 21-4 shows the timing of the internal reset signal generated in the LVD reset mode. 

 

 

R01UH0305EJ0200  Rev.2.00 

 

 

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Jul 04, 2013