Renesas rl78 User Manual
RL78/G1A
CHAPTER 21 VOLTAGE DETECTOR
Figure 21-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation
(Option Byte LVIMDS1, LVIMDS0 = 1, 0) (1/2)
<R>
H
Note 1
Normal
operation
{
Lower limit of operation voltage
LVIMK flag
(set by software)
If a reset is not generated after releasing the mask,
determine that a condition of V
determine that a condition of V
DD
becomes V
DD
≥ V
LVDH
,
clear LVIMD bit to 0, and the MCU shift to normal operation.
INTLVI
LVIIF flag
Internal reset signal
LVD reset signal
POR reset signal
LVIRF flag
LVIMD flag
LVILV flag
LVIOMSK flag
Operation status
LVIF flag
LVISEN flag
(set by software)
Cleared by
software
software
Note 2
Cleared by
software
software
Note 3
Cleared
Cleared
Wait for stabilization by software (400
μs or 5 clocks of f
IL
)
Note 3
Cleared by software
Cleared by
software
software
Time
Normal
operation
RESET
RESET
Save
processing
RESET
Save processing
V
LVDL
V
LVDH
V
POR
= 1.51 V (TYP.)
V
PDR
= 1.50 V (TYP.)
Supply voltage (V
DD
)
Normal
operation
(Notes and Remark are listed on the next page.)
R01UH0305EJ0200 Rev.2.00
765
Jul 04, 2013