Renesas rl78 User Manual

 

RL78/G1A 

CHAPTER  22   SAFETY  FUNCTIONS 

In order to guarantee safety during operation, the IEC61508 standard mandates that important SFRs be protected from 

being overwritten, even if the CPU freezes. 

This SFR guard function is used to protect data in the control registers used by the port function, interrupt function, 

clock control function, voltage detection function, and RAM parity error function. 

If the SFR guard function is specified, writing to the specified SFRs is disabled, but reading from the SFRs can be 

carried out as usual. 

 

This register is used to control the detection of invalid memory access and RAM/SFR guard function. 

GPORT, GINT and GCSC bits are used in SFR guard function. 

The IAWCTL register can be set by an 8-bit memory manipulation instruction. 

Reset signal generation clears this register to 00H. 

 

 

Address: F0078H     After reset: 00H     R/W 

Symbol 

7 6 5 4 3 2 1 0 

IAWCTL 

IAWEN  0 GRAM1 

GRAM0 0 GPORT 

GINT 

GCSC 

 

GPORT 

Control registers of port function guard 

0 

Disabled.  Control registers of port function can be read or written to. 

1 

Enabled.  Writing to control registers of port function is disabled.  Reading is enabled. 

[Guarded SFR] PMxx, PUxx, PIMxx, POMxx, PMCxx, ADPC, PIOR

 

 

GINT 

Registers of interrupt function guard 

0 

Disabled.  Registers of interrupt function can be read or written to. 

1 

Enabled.  Writing to registers of interrupt function is disabled.  Reading is enabled.  

[Guarded SFR] IFxx, MKxx, PRxx, EGPx, EGNx 

 

GCSC 

Control registers of clock control function, voltage detector and RAM parity error detection function guard

0 

Disabled.  Control registers of clock control function, voltage detector and RAM parity error detection 

function can be read or written to. 

1 

Enabled.  Writing to control registers of clock control function, voltage detector and RAM parity error 

detection function is disabled.  Reading is enabled.  

[Guarded SFR] CMC, CSC, OSTS, CKC, PERx, OSMC, LVIM, LVIS, RPECTL 

 

Note  Pxx (Port register) is not guarded. 

 

R01UH0305EJ0200  Rev.2.00 

 

 

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Jul 04, 2013