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Renesas rl78 User Manual

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RL78/G1A 
 
CHAPTER  3   CPU  ARCHITECTURE 
R01UH0305EJ0200  Rev.2.00 
 
 
63  
Jul 04, 2013 
(d)  Auxiliary carry flag (AC)  
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1).  It is reset (0) in all other cases. 
 
(e) In-service 
priority 
flags (ISP1, ISP0)  
This flag manages the priority of acknowledgeable maskable vectored interrupts.  Vectored interrupt requests 
specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers (PRn0L, PRn0H, 
PRn1L, PRn1H, PRn2L, PRn2H) (see 16.3.3) can not be acknowledged.  Actual vectored interrupt request 
acknowledgment is controlled by the interrupt enable flag (IE). 
 
Remark  n = 0, 1 
 
(f)  Carry flag (CY)  
This flag stores overflow and underflow upon add/subtract instruction execution.  It stores the shift-out value upon 
rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. 
 
(3)  Stack pointer (SP)  
This is a 16-bit register to hold the start address of the memory stack area.  Only the internal RAM area can be set as 
the stack area.   
 
Figure 3-9.  Format of Stack Pointer  
 
15
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1
0
0
 
 
In stack addressing through a stack pointer, the SP is decremented ahead of write (save) to the stack memory and is 
incremented after read (restore) from the stack memory. 
 
Cautions 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the SP 
before using the stack. 
 
2. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching 
instruction or a stack area. 
 
3.  Do not allocate RAM addresses which are used as a stack area, a data buffer, a branch 
destination of vector interrupt processing, and a DMA transfer destination/transfer source to the 
area FFE20H to FFEDFH when performing self-programming and rewriting the data flash memory. 
 
4.  Use of the RAM areas of the following products is prohibited when performing self-programming 
and rewriting the data flash memory, because these areas are used for each library. 
 
R5F10ExA (x = 8, B, G):  
FFE20H to FFEDFH 
R5F10ExC (x = 8, B, G, L):   FFE20H to FFEDFH 
R5F10ExD (x = 8, B, G, L):   FFE20H to FFEDFH, FF300H to FF309H 
R5F10ExE (x = 8, B, G, L):   FFE20H to FFEDFH, FEF00H to FF309H 
 
 
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