Renesas rl78 User Manual
RL78/G1A
CHAPTER 28 INSTRUCTION SET
R01UH0305EJ0200 Rev.2.00
833
Jul 04, 2013
28.2 Operation List
Table 28-5. Operation List (1/17)
Notes 1. Number of CPU clocks (f
CLK
) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2.
Number of CPU clocks (f
CLK
) when the code flash memory is accessed, or when the data flash memory is
accessed by an 8-bit instruction.
3. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group
Mnemonic Operands Bytes
Note 1
Note 2
Clocks
Z AC CY
r, #byte
2
1
−
r
← byte
PSW, #byte
3
3
−
PSW
← byte
× ×
×
CS, #byte
3
1
−
CS
← byte
ES, #byte
2
1
−
ES
← byte
!addr16, #byte
4
1
−
(addr16)
← byte
ES:!addr16, #byte
5
2
−
(ES, addr16)
← byte
saddr, #byte
3
1
−
(saddr)
← byte
sfr, #byte
3
1
−
sfr
← byte
[DE+byte], #byte
3
1
−
(DE+byte)
← byte
ES:[DE+byte],#byte 4 2
−
((ES, DE)+byte)
← byte
[HL+byte], #byte
3
1
−
(HL+byte)
← byte
ES:[HL+byte],#byte 4 2
−
((ES, HL)+byte)
← byte
[SP+byte], #byte
3
1
−
(SP+byte)
← byte
word[B], #byte
4
1
−
(B+word)
← byte
ES:word[B], #byte
5
2
−
((ES, B)+word)
← byte
word[C], #byte
4
1
−
(C+word)
← byte
ES:word[C], #byte
5
2
−
((ES, C)+word)
← byte
word[BC], #byte
4
1
−
(BC+word)
← byte
ES:word[BC], #byte
5
2
−
((ES, BC)+word)
← byte
A, r
Note 3
1
1
−
A
← r
r, A
Note 3
1
1
−
r
← A
A, PSW
2
1
−
A
← PSW
PSW, A
2
3
−
PSW
← A
× ×
×
A, CS
2
1
−
A
← CS
CS, A
2
1
−
CS
← A
A, ES
2
1
−
A
← ES
ES, A
2
1
−
ES
← A
A, !addr16
3
1
4
A
← (addr16)
A, ES:!addr16
4
2
5
A
← (ES, addr16)
!addr16, A
3
1
−
(addr16)
← A
ES:!addr16, A
4
2
−
(ES, addr16)
← A
A, saddr
2
1
−
A
← (saddr)
8-bit data
transfer
transfer
MOV
saddr, A
2
1
−
(saddr)
← A
<R>