Renesas rl78 User Manual
RL78/G1A
CHAPTER 29 ELECTRICAL SPECIFICATIONS (T
A
=
−40 to +85°C)
R01UH0305EJ0200 Rev.2.00
873
Jul 04, 2013
(3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(T
A
=
−40 to +85°C, 1.6 V ≤ EV
DD0
≤ V
DD
≤ 3.6 V, V
SS
= EV
SS0
= 0 V)
HS
Note 1
LS
Note 2
LV
Note 3
Parameter Symbol
Conditions
MIN.
MAX.
MIN.
MAX. MIN. MAX.
Unit
2.7 V
≤ EV
DD0
≤ 3.6 V t
KCY1
≥ 4/f
CLK
125
500 1000 ns
2.4 V
≤ EV
DD0
≤ 3.6 V t
KCY1
≥ 4/f
CLK
250
500 1000
ns
1.8 V
≤ EV
DD0
≤ 3.6 V t
KCY1
≥ 4/f
CLK
500
500 1000
ns
1.7 V
≤ EV
DD0
≤ 3.6 V t
KCY1
≥ 4/f
CLK
1000
1000 1000
ns
SCKp cycle time
t
KCY2
1.6 V
≤ EV
DD0
≤ 3.6 V t
KCY1
≥ 4/f
CLK
−
1000 1000 ns
2.7 V
≤ EV
DD0
≤ 3.6 V
t
KCY2
/2
−18
t
KCY2
/2
−50
t
KCY2
/2
−50
ns
2.4 V
≤ EV
DD0
≤ 3.6 V
t
KCY2
/2
−38
t
KCY2
/2
−50
t
KCY2
/2
−50
ns
1.8 V
≤ EV
DD0
≤ 3.6 V
t
KCY2
/2
−50
t
KCY2
/2
−50
t
KCY2
/2
−50
ns
1.7 V
≤ EV
DD0
≤ 3.6 V
t
KCY2
/2
−100
t
KCY2
/2
−100
t
KCY2
/2
−100
ns
SCKp high-/low-level
width
t
KH2
,
t
KL2
1.6 V
≤ EV
DD0
≤ 3.6 V
−
t
KCY2
/2
−100
t
KCY2
/2
−100
ns
2.7 V
≤ EV
DD0
≤
3.6
V
44 110
110 ns
2.4 V
≤ EV
DD0
≤
3.6
V
75 110
110 ns
1.8 V
≤ EV
DD0
≤
3.6
V
110
110
110 ns
1.7 V
≤ EV
DD0
≤
3.6
V
220
220
220 ns
SIp setup time
(to SCKp
↑)
Note 4
t
SIK2
1.6 V
≤ EV
DD0
≤ 3.6 V
−
220
220 ns
1.7 V
≤ EV
DD
≤
3.6
V
19 19 19 ns
SIp hold time
(from SCKp
↑)
Note 4
t
KSI2
1.6 V
≤ EV
DD
≤ 3.6 V
−
19 19 ns
1.7 V
≤ EV
DD
≤ 3.6 V C = 30 pF
Note 6
25 25 25 ns
Delay time from SCKp
↓
to SOp output
Note 5
t
KSO2
1.6 V
≤ EV
DD
≤ 3.6 V C = 30 pF
Note 6
−
25 25 ns
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time or SIp hold time
becomes “from SCKp
↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp
↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
6. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark p: CSI number (p = 00, 01, 10, 11, 20, 21), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM numbers (g = 0, 1)