Renesas rl78 User Manual
RL78/G1A
CHAPTER 29 ELECTRICAL SPECIFICATIONS (T
A
=
−40 to +85°C)
R01UH0305EJ0200 Rev.2.00
879
Jul 04, 2013
(6) Communication at different potential (1.8 V, 2.5 V) (UART mode) (dedicated baud rate generator output) (1/2)
(T
A
=
−40 to +85°C, 1.8 V ≤ EV
DD0
≤ V
DD
≤ 3.6 V, V
SS
= EV
SS0
= 0 V)
HS
Note 1
LS
Note 2
LV
Note 3
Parameter Symbol
Conditions
MIN. MAX. MIN. MAX. MIN. MAX.
Unit
f
MCK
/6
f
MCK
/6 f
MCK
/6
bps
2.7 V
≤ EV
DD0
≤ 3.6 V,
2.3 V
≤ V
b
≤ 2.7 V
Theoretical value of the
maximum transfer rate
f
MCK
= f
CLK
Note 7
5.3
1.3 0.6
Mbps
f
MCK
/6 f
MCK
/6 f
MCK
/6
bps
Transfer
rate
Note 4
Reception
1.8 V
≤ EV
DD0
< 3.3 V,
1.6 V
≤ V
b
≤ 2.0 V
Note 5
Theoretical value of the
maximum transfer rate
f
MCK
= f
CLK
Note 7
5.3
Note 6
1.3 0.6
Mbps
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4. Transfer rate in the SNOOZE mode is 4800 bps.
5. Use it with EV
DD0
≥V
b
.
6. The following conditions are required for low-voltage interface when EV
DD0
< V
DD
.
2.4 V
≤ EV
DD0
< 2.7 V : MAX. 2.6 Mbps
1.8 V
≤ EV
DD0
< 2.4 V : MAX. 1.3 Mbps
7. f
CLK
in each operating mode is as below.
HS (high-speed main) mode: f
CLK
= 32 MHz
LS (low-speed main) mode: f
CLK
= 8 MHz
LV
(low-voltage main) mode: f
CLK
= 4 MHz
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V
DD
tolerance (When 25- to
48-pin products)/EV
DD
tolerance (When 64-pin products)) mode for the TxDq pin by using port input
mode register g (PIMg) and port output mode register g (POMg). For V
IH
and V
IL
, see the DC
characteristics with TTL input buffer selected.
Remarks 1. V
b
[V]: Communication line voltage
2.
q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1)
3.
f
MCK
: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10, 11)
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