Renesas rl78 User Manual
RL78/G1A
CHAPTER 29 ELECTRICAL SPECIFICATIONS (T
A
=
−40 to +85°C)
R01UH0305EJ0200 Rev.2.00
884
Jul 04, 2013
(8) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock output) (2/2)
(T
A
=
−40 to +85°C, 1.8 V ≤ EV
DD0
≤ V
DD
≤ 3.6 V, V
SS
= EV
SS0
= 0 V)
HS
Note 1
LS
Note 2
LV
Note 3
Parameter Symbol
Conditions
MIN.
MAX.
MIN. MAX. MIN. MAX.
Unit
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V,
C
b
= 30 pF, R
b
= 2.7 k
Ω
177
479 479 ns
SIp setup time
(to SCKp
(to SCKp
↑)
Note 4
t
SIK1
1.8 V
≤ EV
DD0
< 3.3 V, 1.6 V
≤ V
b
≤ 2.0 V
Note 6
,
C
b
= 30 pF, R
b
= 5.5 k
Ω
479
479 479 ns
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V,
C
b
= 30 pF, R
b
= 2.7 k
Ω
19
19 19 ns
SIp hold time
(from SCKp
(from SCKp
↑)
Note 4
t
KSI1
1.8 V
≤ EV
DD0
< 3.3 V, 1.6 V
≤ V
b
≤ 2.0 V
Note 6
,
C
b
= 30 pF, R
b
= 5.5 k
Ω
19
19 19 ns
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V,
C
b
= 30 pF, R
b
= 2.7 k
Ω
195
195 195
ns
Delay time from SCKp
↓ to
SOp output
Note 4
t
KSO1
1.8 V
≤ EV
DD0
< 3.3 V, 1.6 V
≤ V
b
≤ 2.0 V
Note 6
,
C
b
= 30 pF, R
b
= 5.5 k
Ω
483
483 483
ns
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V,
C
b
= 30 pF, R
b
= 2.7 k
Ω
44
110 110 ns
SIp setup time
(to SCKp
(to SCKp
↓)
Note 5
t
SIK1
1.8 V
≤ EV
DD0
< 3.3 V, 1.6 V
≤ V
b
≤ 2.0 V
Note 6
,
C
b
= 30 pF, R
b
= 5.5 k
Ω
110
110 110 ns
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V,
C
b
= 30 pF, R
b
= 2.7 k
Ω
19
19 19 ns
SIp hold time
(from SCKp
(from SCKp
↓)
Note 5
t
KSI1
1.8 V
≤ EV
DD0
< 3.3 V, 1.6 V
≤ V
b
≤ 2.0 V
Note 6
,
C
b
= 30 pF, R
b
= 5.5 k
Ω
19
19 19 ns
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V,
C
b
= 30 pF, R
b
= 2.7 k
Ω
25
25 25
ns
Delay time from SCKp
↑ to
SOp output
Note 5
t
KSO1
1.8 V
≤ EV
DD0
< 3.3 V, 1.6 V
≤ V
b
≤ 2.0 V
Note 6
,
C
b
= 30 pF, R
b
= 5.5 k
Ω
25
25 25
ns
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
5. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
6. Use it with EV
DD0
≥ V
b
.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V
DD
tolerance (When 25- to
48-pin products)/EV
DD
tolerance (When 64-pin products)) mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg). For V
IH
and V
IL
, see the DC
characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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