Renesas rl78 User Manual
RL78/G1A
CHAPTER 29 ELECTRICAL SPECIFICATIONS (T
A
=
−40 to +85°C)
R01UH0305EJ0200 Rev.2.00
891
Jul 04, 2013
(10) Communication at different potential (1.8 V, 2.5 V) (simplified I
2
C mode) (2/2)
(T
A
=
−40 to +85°C, 1.8 V ≤ EV
DD0
≤ V
DD
≤ 3.6 V, V
SS
= EV
SS0
= 0 V)
HS
Note 1
LS
Note 2
LV
Note 3
Parameter Symbol
Conditions
MIN.
MAX.
MIN.
MAX. MIN. MAX.
Unit
2.7 V
≤ EV
DD0
≤ 3.6 V,
2.3 V
≤ V
b
≤ 2.7 V,
C
b
= 50 pF, R
b
= 2.7 k
Ω
1/f
MCK
+
135
Note 6
1/f
MCK
+
190
Note 6
1/f
MCK
+
190
Note 6
ns
2.7 V
≤ EV
DD0
≤ 3.6 V,
2.3 V
≤ V
b
≤ 2.7 V,
C
b
= 100 pF, R
b
= 2.7 k
Ω
1/f
MCK
+
190
Note 6
1/f
MCK
+
190
Note 6
1/f
MCK
+
190
Note 6
ns
Data setup time (reception)
t
SU:DAT
1.8 V
≤ EV
DD0
< 3.3 V,
1.6 V
≤ V
b
≤ 2.0 V
Note 5
,
C
b
= 100 pF, R
b
= 5.5 k
Ω
1/f
MCK
+
190
Note 6
1/f
MCK
+
190
Note 6
1/f
MCK
+
190
Note 6
ns
2.7 V
≤ EV
DD0
≤ 3.6 V,
2.3 V
≤ V
b
≤ 2.7 V,
C
b
= 50 pF, R
b
= 2.7 k
Ω
0 305 0 305 0 305
ns
2.7 V
≤ EV
DD0
≤ 3.6 V,
2.3 V
≤ V
b
≤ 2.7 V,
C
b
= 100 pF, R
b
= 2.7 k
Ω
0 355 0 355 0 355
ns
Data hold time (transmission)
t
HD:DAT
1.8 V
≤ EV
DD0
< 3.3 V,
1.6 V
≤ V
b
≤ 2.0 V
Note 5
,
C
b
= 100 pF, R
b
= 5.5 k
Ω
0 405 0 405 0 405
ns
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4. The value must also be f
CLK
/4 or lower.
5.
Use it with EV
DD0
≥ V
b
.
6.
Set the f
MCK
value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the TTL input buffer and the N-ch open drain output (V
DD
tolerance (When 25- to 48-pin
products)/EV
DD
tolerance (When 64-pin products)) mode for the SDAr pin and the N-ch open drain
output (V
DD
tolerance (When 25- to 48-pin products)/EV
DD
tolerance (When 64-pin products)) mode for
the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For
V
IH
and V
IL
, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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