Renesas rl78 User Manual
RL78/G1A
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS T
A
=
−40 to +105°C)
R01UH0305EJ0200 Rev.2.00
937
Jul 04, 2013
(7) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (slave mode, SCKp... external clock input)
(T
A
=
−40 to +105°C, 2.4 V ≤ EV
DD0
≤ V
DD
≤ 3.6 V, V
SS
= EV
SS0
= 0 V)
Parameter Symbol
Conditions
MIN.
TYP.
MAX.
Unit
24 MHz < f
MCK
40/f
MCK
ns
20 MHz < f
MCK
≤ 24 MHz
32/f
MCK
ns
16 MHz < f
MCK
≤ 20 MHz
28/f
MCK
ns
8 MHz < f
MCK
≤ 16 MHz
24/f
MCK
ns
4 MHz < f
MCK
≤ 8 MHz
16/f
MCK
ns
2.7 V
≤ EV
DD0
≤ 3.6 V,
2.3 V
≤ V
b
≤ 2.7 V
f
MCK
≤ 4 MHz
12/f
MCK
ns
24 MHz < f
MCK
96/f
MCK
ns
20 MHz < f
MCK
≤ 24 MHz
72/f
MCK
ns
16 MHz < f
MCK
≤ 20 MHz
64/f
MCK
ns
8 MHz < f
MCK
≤ 16 MHz
52/f
MCK
ns
4 MHz < f
MCK
≤ 8 MHz
32/f
MCK
ns
SCKp cycle time
Note 1
t
KCY2
2.4 V
≤ EV
DD0
< 3.3 V,
1.6 V
≤ V
b
≤ 2.0 V
f
MCK
≤ 4 MHz
20/f
MCK
ns
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V
t
KCY2
/2
− 36
ns
SCKp high-/low-level width
t
KH2
,
t
KL2
2.4 V
≤ EV
DD0
< 3.3 V, 1.6 V
≤ V
b
≤ 2.0 V
t
KCY2
/2
−
100
ns
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V
1/f
MCK
+ 40
SIp setup time
(to SCKp
↑)
Note 2
t
SIK2
2.4 V
≤ EV
DD0
< 3.3 V, 1.6 V
≤ V
b
≤ 2.0 V
1/f
MCK
+ 60
ns
SIp hold time
(from SCKp
↑)
Note 2
t
KSI2
1/f
MCK
+ 62
ns
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V,
C
b
= 30 pF, R
b
= 2.7 k
Ω
2/f
MCK
+
428
ns
Delay time from SCKp
↓ to
SOp output
Note 3
t
KSO2
2.4 V
≤ EV
DD0
< 3.3 V, 1.6 V
≤ V
b
≤ 2.0 V,
C
b
= 30 pF, R
b
= 5.5 k
Ω
2/f
MCK
+
1146
ns
Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time or SIp hold time
becomes “from SCKp
↓“ when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp
↑“ when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (V
DD
tolerance
(When 25- to 48-pin products)/EV
DD
tolerance (When 64-pin products)) mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg). For V
IH
and V
IL
, see the DC
characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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