Avaya 03-300430 User Manual
SYNC (Port-Network Synchronization)
Issue 1 June 2005
2173
Bus Clock Test #148 passes successfully. If Test #148 fails with an Error Code 2 through
32, refer to the TDM-CLK (TDM Bus Clock) Maintenance documentation to resolve the
problem. If not, continue with the following steps.
32, refer to the TDM-CLK (TDM Bus Clock) Maintenance documentation to resolve the
problem. If not, continue with the following steps.
3. Replace the primary and secondary (if administered) DS1 Interface circuit packs.
4. Check for an error logged against the primary or secondary DS1 board. If there is an
error, follow the DS1 section to resolve the errors. If there is not, enter enable sync,
and wait for two to five minutes for the primary sync source to come on-line.
f. Error Type 2049: the slave Tone-Clock circuit pack is experiencing loss of signal. Refer to
note (i) for error resolution steps.
The following steps should be executed to resolve error 2049 and 2305:
1. Check for timing loops, and resolve any loops that exist.
2. Error 2049:
●
Test the Tone-Clock circuit packs in the master and slave port networks using test
tone/clock location long. Check the Error Log for TDM-CLK errors and verify
tone/clock location long. Check the Error Log for TDM-CLK errors and verify
that TDM Bus Clock Test #148 passes successfully. If Test #148 fails with an Error
Code 2 through 32, refer to
Code 2 through 32, refer to
on page 2252 to resolve the
problem. If not, continue with the following steps.
●
If the system synchronization reference is a Tone-Clock circuit pack and the master
Tone-Clock circuit pack fails TDM Bus Clock Test #150, follow the steps listed in
Tone-Clock circuit pack fails TDM Bus Clock Test #150, follow the steps listed in
on page 2252 to replace the master Tone-Clock circuit
pack.
●
If the system synchronization reference is a DS1 interface circuit pack and the master
Tone-Clock circuit pack fails TDM Bus Clock Test #150, the primary or secondary (if
administered) synchronization references are not providing valid timing signals for the
system. Check the system synchronization references administered, and follow the
steps outlined in note (a) if the primary synchronization reference is providing timing
for the system or note (c) if the secondary synchronization reference is providing
timing for the system.
Tone-Clock circuit pack fails TDM Bus Clock Test #150, the primary or secondary (if
administered) synchronization references are not providing valid timing signals for the
system. Check the system synchronization references administered, and follow the
steps outlined in note (a) if the primary synchronization reference is providing timing
for the system or note (c) if the secondary synchronization reference is providing
timing for the system.
●
If the slave Tone-Clock circuit pack fails the TDM Bus Clock Test #150 but the master
Tone-Clock does not fail this test, the master Tone-Clock circuit pack must be
replaced.
Tone-Clock does not fail this test, the master Tone-Clock circuit pack must be
replaced.
If SLIP errors remain follow SLIP ANALYSIS.
3. Error 2305:
●
If the problem persists, replace the Tone-Clock circuit pack in the slave port network.
Follow the steps listed in
Follow the steps listed in
Tone-Clock circuit pack.
g. Noise on the DS1 line can cause transient alarms on synchronization. Therefore, when a
synchronization problem occurs causing Error Types 1, 257, or 513, a WRN alarm is first
raised for 15 to 20 minutes before the alarm is upgraded to a MAJOR or MINOR alarm.
raised for 15 to 20 minutes before the alarm is upgraded to a MAJOR or MINOR alarm.