Avaya 03-300430 User Manual

Note:

Replacing the Tone-Clock circuit pack or the IPSI requires a special procedure 
described in the documentation for 

That section also describes the LED displays for these circuit packs.

The Time Division Multiplex (TDM) Bus Clock resides on the Tone-Clock circuit, providing 
clocking signals both for the TDM bus and the LAN Bus. The Tone-Clock circuit is a critical 
component in the system and is necessary to ensure the operation of every port circuit pack in 
the system. The TDM buses of every EPNs is synchronized together. The system timing 
reference can be derived internally from the Tone-Clock circuit in any PN, or from an external 
(off-board) timing reference. Currently, the TDM bus Clock supports synchronizing the TDM bus 
with interface rates from Digital Signal 1 (DS1) facilities as primary or primary and secondary 
references, (

: and from Stratum-3 clock (STRAT-3) facilities. Only the TN780 

tone-clock supports a Stratum-3 clock.)
Moreover, the TN2314 Processor/Tone-Clock circuit pack aids in monitoring and selecting 
synchronization references. The TN2314 Processor/Tone-Clock circuit pack, after detecting that 
the external source of timing is not valid, will automatically begin its escalation procedure, 
according to the facilities administered. In the following table, successive losses of signal cause 
escalation from left to right.
Switching back to a DS1 source is handled by synchronization maintenance, once any problems 

with it are corrected and tested.

: However, once synchronization has been switched to the internal timing source of 

the master Tone-Clock circuit, switching back to a Stratum-3 clock must be initiated by a 

technician after the external reference has been repaired.

TDM-CLK

MAJ

test tone-clock location short TDM bus Clock

TDM-CLK

MIN

test tone-clock location short TDM bus Clock

TDM-CLK

WRN

TDM bus Clock

MASTER

Stratum-3 clock

Source “A”

Source “B”

Local 

oscillator

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